scholarly journals Circuit Optimization For Transmission Gate Master Slave Flip-Flops

2013 ◽  
Vol 11 (3) ◽  
pp. 2387-2392
Author(s):  
Maheswari Muraboyina ◽  
Dr.S. Govindarajulu

In this work, when dealing with transmission-gate-based master-slave (TGMS) flip-flops (FFs), a reconsideration of the classical approach for the delay, power, and area minimization is worthwhile to improve the performance in high-speed designs[1]. In particular, by splitting such FFs into two sections that are separately optimized and then reconciling the results, the emerging design always outperforms the one resulting from the employment of a classical Logical Effort procedure assuming such FFs as a whole continuous path[1]. Simulations have been performed at transistor level on several well-known TGMS FFs, designed in 65-nm and 90nm technologies using Microwind3.1 CAD tool, and the results have been compared to validate the correctness of such a procedure and of the underlying assumptions. Significant improvements have been found on delay, power and on area occupation, thus showing that this approach allows correctly dealing with the actual path in such circuits and hence to more properly steering the design towards the achievement of efficiency in the high-speed region[1]. epaE� n � �� RGMCET, Nandyal,[email protected] 

1956 ◽  
Vol 60 (547) ◽  
pp. 459-475 ◽  
Author(s):  
E. G. Broadbent

SummaryA review is given of developments in the field of aeroelasticity during the past ten years. The effect of steadily increasing Mach number has been two-fold: on the one hand the aerodynamic derivatives have changed, and in some cases brought new problems, and on the other hand the design for higher Mach numbers has led to thinner aerofoils and more slender fuselages for which the required stiffness is more difficult to provide. Both these aspects are discussed, and various methods of attack on the problems are considered. The relative merits of stiffness, damping and massbalance for the prevention of control surface flutter are discussed. A brief mention is made of the recent problems of damage from jet efflux and of the possible aeroelastic effects of kinetic heating.


Author(s):  
Ce Yang ◽  
Ben Zhao ◽  
C. C. Ma ◽  
Dazhong Lao ◽  
Mi Zhou

Two different inlet configurations, including a straight pipe and a bent pipe, were experimentally tested and numerically simulated using a high-speed, low-mass flow centrifugal compressor. The pressure ratios of the compressor with the two inlet configurations were tested and then compared to illustrate the effect of the bent inlet pipe on the compressor. Furthermore, different circumferential positions of the bent inlet pipe relative to the volute are discussed for two purposes. One purpose is to describe the changes in the compressor performance that result from altering the circumferential position of the bent inlet pipe relative to the volute. This change in performance may be the so-called clocking effect, and its mechanism is different from the one in multistage turbomachinery. The other purpose is to investigate the unsteady flow for different matching states of the bent inlet pipe and volute. Thus, the frequency spectrum of unsteady pressure fluctuation was applied to analyze the aerodynamic response. Compared with the straight inlet pipe, the experimental results show that the pressure ratio is modulated and that the choke point is shifted in the bent inlet pipe. Similarly, the pressure ratio can be influenced by altering the circumferential position of the bent inlet pipe relative to the volute, which may have an effect on the unsteady pressure in the rotor section. Therefore, the magnitude of interest spectral frequency is significantly changed by clocking the bent inlet pipe.


2014 ◽  
Vol 137 (4) ◽  
Author(s):  
David Tan ◽  
Yuanchao Li ◽  
Ian Wilkes ◽  
Rinaldo L. Miorini ◽  
Joseph Katz

A new optically index matched facility has been constructed to investigate tip flows in compressor-like settings. The blades of the one and a half stage compressor have the same geometry, but lower aspect ratio as the inlet guide vanes (IGVs) and the first stage of the low-speed axial compressor (LSAC) facility at NASA Glenn. With transparent blades and casings, the new setup enables unobstructed velocity measurements at any point within the tip region and is designed to facilitate direct measurements of effects of casing treatments on the flow structure. We start with a smooth endwall casing. High speed movies of cavitation and time-resolved PIV measurements have been used to characterize the location, trajectory, and behavior of the tip leakage vortex (TLV) for two flow rates, the lower one representing prestall conditions. Results of both methods show consistent trends. As the flow rate is reduced, TLV rollup occurs further upstream, and its initial orientation becomes more circumferential. At prestall conditions, the TLV is initially aligned slightly upstream of the rotor passage, and subsequently forced downstream. Within the passage, the TLV breaks up into a large number of vortex fragments, which occupy a broad area. Consequently, the cavitation in the TLV core disappears. With decreasing flow rate, this phenomenon becomes more abrupt, occurs further upstream, and the fragments occupy a larger area.


2018 ◽  
Vol 18 (3) ◽  
pp. 401-405
Author(s):  
Jomo Kwame Sundaram

Of the ten fastest growing economies since 1960, eight are in East Asia. As Haggard (2018) aptly demonstrates for Northeast Asia, two explanations account for this exceptional regional performance. On the one hand, neo-liberals committed to an Anglo-American night-watchman state (Krueger 1978; Bhagwati 1978; Edwards 1993; World Bank 1993; Pack and Saggi 2006) attribute performance to macroeconomic stability, provision of public goods, and openness to trade and investment. On the other hand, a heterodox group (Johnson 1982; Amsden 1989; Wade 1990/2004; Chang 2002, 1994; Rodrik 1995; Evans 1995; Lin 2009) focuses on market and coordination failures and the need for states to adopt pragmatic, ‘trial and error’ and selective approaches to high-speed growth. In this latter view, the strong developmental states of Northeast Asia used their embedded autonomy viz the private sector to overcome market and coordination failures to usher in rapid growth and technological catch-up.


Author(s):  
M. Naga Gowtham Et.al

In this paper, a hybrid 1-bit adder and 1-bit Subtractor designs are implemented. The hybrid adder circuit is constructed using CMOS (complementary metal oxide semiconductor) logic along with pass transistor logic. The design can be extended 16 and 32 bits lately. The proposed full adder circuit is compared with the existing conventional adders in terms of power, delay and area in order to obtain a better circuit that serves the present day needs of people. The existing 1-bit hybrid adder uses EXNOR logic combined with the transmission gate logic. For a supply voltage of 1.8V the average power consumption (4.1563 µW) which is extremely low with moderately low delay (224 ps) resulting because of the deliberate incorporation of very weak CMOS inverters coupled with strong transmission gates. At 1.2V supply the power and delay were recorded to be 1.17664 µW and 91.3 ps. The design was implemented using 1-bit which can also be extended into a 32-bit design later. The designed implementation offers a better performance in terms of power and speed compared to the existing full adder design styles. The circuits were implemented in DSCH2 and Microwind tools respectively. The parameters such as power, delay, layout area and speed of the proposed circuit design is compared with pass transistor logic, adiabatic logic, transmission gate adder and so on. The circuit is also designed with a decrease in transistors in order to get the better results. Full Subtractor, a combinational digital circuit which performs 1-bit subtraction with borrow in is designed as a part of this project. The main aim behind this part of the project is to design a 1-bit full Subtractor using CMOS technology with reduced number of transistors and hence the efficiency in terms of area, power and speed have been calculated is designed using 8,10,15and 16 transistors. The parameters were calculated in each case and the results have been tabulated.


Author(s):  
M. Naga Gowtham, P.S Hari Krishna Reddy, K Jeevitha, K Hari Kishore, E Raghuveera, Shaik Razia

In this paper, a hybrid 1-bit adder and 1-bit Subtractor designs are implemented. The hybrid adder circuit is constructed using CMOS (complementary metal oxide semiconductor) logic along with pass transistor logic. The design can be extended 16 and 32 bits lately. The proposed full adder circuit is compared with the existing conventional adders in terms of power, delay and area in order to obtain a better circuit that serves the present day needs of people. The existing 1-bit hybrid adder uses EXNOR logic combined with the transmission gate logic. For a supply voltage of 1.8V the average power consumption (4.1563 µW) which is extremely low with moderately low delay (224 ps) resulting because of the deliberate incorporation of very weak CMOS inverters coupled with strong transmission gates. At 1.2V supply the power and delay were recorded to be 1.17664 µW and 91.3 ps. The design was implemented using 1-bit which can also be extended into a 32-bit design later. The designed implementation offers a better performance in terms of power and speed compared to the existing full adder design styles. The circuits were implemented in DSCH2 and Microwind tools respectively. The parameters such as power, delay, layout area and speed of the proposed circuit design is compared with pass transistor logic, adiabatic logic, transmission gate adder and so on. The circuit is also designed with a decrease in transistors in order to get the better results. Full Subtractor, a combinational digital circuit which performs 1-bit subtraction with borrow in is designed as a part of this project. The main aim behind this part of the project is to design a 1-bit full Subtractor using CMOS technology with reduced number of transistors and hence the efficiency in terms of area, power and speed have been calculated is designed using 8,10,15and 16 transistors. The parameters were calculated in each case and the results have been tabulated.


1961 ◽  
Vol EC-10 (3) ◽  
pp. 426-438 ◽  
Author(s):  
N. S. Prywes ◽  
H. Lukoff ◽  
J. Schwarz

2010 ◽  
Vol 297-301 ◽  
pp. 396-401
Author(s):  
Mehrdad Vahdati ◽  
E. Azimi ◽  
Ali Shokuhfar

Air Spindles have been used in ultra precision machines for several years due to their advantages such as high speed rotation, low friction, and low vibration, [1]. Air spindles are widely used in these machines for producing precise work pieces. Although, spindles function on a very complicated theoretical basis, [2, 3], their structure is very simple and consists of mainly a rotor and a stator. The rotor/stator could be made of different shapes. A cylindrical shape is the one commonly in use. The spindle designed in this work has a spherical configuration. It has been designed so that it could be moved without application of electric motor and only by a wind turbine system, [4]. The spindle studied in this research uses compressed air for rotor suspension, and has an air turbine for rotating its shaft. A thin air film acts as bearing layer between rotor and stator. In design procedure, operation parameters such as air inlet pressure for turbine, air inlet pressure for bearing, diameter of turbine nuzzles, diameter of bearing nuzzles, clearance between rotor and stator and etc. have been considered, [5]. A prototype spindle has been manufactured using design criteria. The influence of above mentioned parameters have been recognized through experiments.


2018 ◽  
Vol 842 ◽  
pp. 381-394 ◽  
Author(s):  
Marco E. Rosti ◽  
Luca Brandt ◽  
Alfredo Pinelli

The effect of the variations of the permeability tensor on the close-to-the-wall behaviour of a turbulent channel flow bounded by porous walls is explored using a set of direct numerical simulations. It is found that the total drag can be either reduced or increased by more than 20 % by adjusting the permeability directional properties. Drag reduction is achieved for the case of materials with permeability in the vertical direction lower than the one in the wall-parallel planes. This configuration limits the wall-normal velocity at the interface while promoting an increase of the tangential slip velocity leading to an almost ‘one-component’ turbulence where the low- and high-speed streak coherence is strongly enhanced. On the other hand, strong drag increase is found when high wall-normal and low wall-parallel permeabilities are prescribed. In this condition, the enhancement of the wall-normal fluctuations due to the reduced wall-blocking effect triggers the onset of structures which are strongly correlated in the spanwise direction, a phenomenon observed by other authors in flows over isotropic porous layers or over ribletted walls with large protrusion heights. The use of anisotropic porous walls for drag reduction is particularly attractive since equal gains can be achieved at different Reynolds numbers by rescaling the magnitude of the permeability only.


Author(s):  
Nakul C. Kubsad

Abstract: Full adder circuit is one among the fundamental and necessary digital part. The full adder is be a part of microprocessors, digital signal processors etc. It's needed for the arithmetic and logical operations. Full adder design enhancements are necessary for recent advancement. The requirement of an adder cell is to provide high speed, consume low power and provide high voltage swing. This paper analyses and compares 3 adders with completely different logic designs (Conventional, transmission gate & pseudo NMOS) for transistor count, power dissipation and delay. The simulation is performed in Cadence virtuoso tool with accessible GPDK – 180nm kit. Transmission gate full adder has sheer advantage of high speed, fewer space and also it shows higher performance in terms of delay. Keywords: Delay, power dissipation, voltage, transistor sizing.


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