scholarly journals FIN-FET BASED HIGH GAIN OP-AMP WITH SLEW RATE ENHANCEMENT IN 45-NM REGIME

2020 ◽  
Vol 6 (7) ◽  
pp. 27-33
Author(s):  
Nagendra Tiwari ◽  
Bharati Chourasia
Keyword(s):  
Power Consumption ◽  
Supply Voltage ◽  
High Gain ◽  
Silicon On Insulator ◽  
Slew Rate ◽  
Video Signals ◽  
Op Amp ◽  
Dynamic Biasing ◽  
Unity Gain ◽  
Two Stages

In this paper dynamic biasing technique is used for the enhancing the slew rate of the designed Op-Amp. The proposed FinFET based Op-Amp has been verified through Hspice simulator in the standard 45nm Silicon on Insulator FinFET library. The proposed op amp has two stages Miller compensated configuration. A biasing circuit (DSB circuit) is used for dynamic switching of the biasing voltage of the op amp. This leads to lower power consumption, wide ICMR range, and high gain stability. The proposed op amp has a power consumption of 661.83 μW. It has a dual supply voltage of -1.0V and 1.0V. The input common mode range (ICMR) is -800 mV to +900 mV. The Op-Amp has a slew rate of 1.5 KV/μs. Voltage gain of the op amp is 90.4dB. Due to the use of SOI FINFET devices the op amp has relatively less leakage current as compared to similar bulk MOSFET device op amps. The op amp has unity gain bandwidth of 1.27 GHz. Thus, it can be used to transmission and processing of audio and video signals.

Design of High Gain Folded Cascode OTA-Based Transconductance–Capacitance Loop Filter for PLL Applications

2021 ◽  
pp. 2150263
Author(s):  
Priti Gupta ◽  
Sanjay Kumar Jana
Keyword(s):  
Power Consumption ◽  
Supply Voltage ◽  
High Gain ◽  
Cmos Process ◽  
Operational Transconductance Amplifier ◽  
Loop Filter ◽  
Transconductance Amplifier ◽  
Dc Gain ◽  
Unity Gain ◽  
Folded Cascode

This paper deals with the designing of low-power transconductance–capacitance-based loop filter. The folded cascode-based operational transconductance amplifier (OTA) is designed in this paper with the help of quasi-floating bulk MOSFET that achieved the DC gain of 88.61[Formula: see text]dB, unity gain frequency of 97.86[Formula: see text]MHz and power consumption of 430.62[Formula: see text][Formula: see text]W. The proposed OTA is compared with the exiting OTA structure which showed 19.50% increase in DC gain and 15.11% reduction in power consumption. Further, the proposed OTA is used for the designing of transconductance–capacitance-based loop filter that has been operated at [Formula: see text]3[Formula: see text]dB cut-off frequency of 30.12[Formula: see text]MHz with the power consumption of 860.90[Formula: see text][Formula: see text]W at the supply voltage of [Formula: see text][Formula: see text]V. The transistor-level simulation has been done in 0.18[Formula: see text][Formula: see text]m CMOS process.

scholarly journals A Novel OTA Architecture Exploiting Current Gain Stages to Boost Bandwidth and Slew-Rate

Electronics ◽  
2021 ◽  
Vol 10 (14) ◽  
pp. 1638
Author(s):  
Francesco Centurelli ◽  
Riccardo Della Sala ◽  
Pietro Monsurrò ◽  
Giuseppe Scotti ◽  
Alessandro Trifiletti
Keyword(s):  
Power Consumption ◽  
Supply Voltage ◽  
Current Gain ◽  
Small Signal ◽  
Slew Rate ◽  
Large Signal ◽  
Current Mirrors ◽  
Order Of Magnitude ◽  
Unity Gain ◽  
Architecture And Design

A novel architecture and design approach which make it possible to boost the bandwidth and slewrate performance of operational transconductance amplifiers (OTAs) are proposed and employed to design a low-power OTA with top-of-class small-signal and large-signal figures of merit (FOMs). The proposed approach makes it possible to enhance the gain, bandwidth and slew-rate for a given power consumption and capacitive load, achieving more than an order of magnitude better performance than a comparable conventional folded cascode amplifier. Current mirrors with gain and a push–pull topology are exploited to achieve symmetrical sinking and sourcing output currents, and hence class-AB behavior. The resulting OTA was implemented using the 130 nm STMicroelectronics process, with a supply voltage of 1 V and a power consumption of only 1 µW. Simulations with a 200 pF load capacitance showed a gain of 92 dB, a unity-gain frequency of 141 kHz, and a peak slew-rate of 30 V/ms, with a phase margin of 80°, and good noise, PSRR and CMRR performance. The small-signal and large-signal current and power FOMs are the highest reported in the literature for comparable amplifiers. Extensive parametric and Monte Carlo simulations show that the OTA is robust against process, supply voltage and temperature (PVT) variations, as well as against mismatches.

A LOW POWER CRYOGENIC CMOS ROIC DESIGN FOR 512 × 512 IRFPA

2013 ◽  
Vol 22 (10) ◽  
pp. 1340033 ◽  
Author(s):  
HONGLIANG ZHAO ◽  
YIQIANG ZHAO ◽  
YIWEI SONG ◽  
JUN LIAO ◽  
JUNFENG GENG
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Integrated Circuit ◽  
High Performance ◽  
Supply Voltage ◽  
Cmos Technology ◽  
High Gain ◽  
Readout Integrated Circuit ◽  
Chip Area ◽  
Operating Modes

A low power readout integrated circuit (ROIC) for 512 × 512 cooled infrared focal plane array (IRFPA) is presented. A capacitive trans-impedance amplifier (CTIA) with high gain cascode amplifier and inherent correlated double sampling (CDS) configuration is employed to achieve a high performance readout interface for the IRFPA with a pixel size of 30 × 30 μm2. By optimizing column readout timing and using two operating modes in column amplifiers, the power consumption is significantly reduced. The readout chip is implemented in a standard 0.35 μm 2P4M CMOS technology. The measurement results show the proposed ROIC achieves a readout rate of 10 MHz with 70 mW power consumption under 3.3 V supply voltage from 77 K to 150 K operating temperature. And it occupies a chip area of 18.4 × 17.5 mm2.

A QFGMOS-Based gm-Boosted and Adaptively Biased Two-Stage Amplifier Offering Very High Gain and High Bandwidth

2021 ◽  
pp. 2250056
Author(s):  
Urvashi Bansal ◽  
Abhilasha Bakre ◽  
Prem Kumar ◽  
Devansh Yadav ◽  
Mohit Kumar ◽  
...  
Keyword(s):  
Low Voltage ◽  
Cmos Technology ◽  
High Gain ◽  
Open Loop ◽  
Slew Rate ◽  
Two Stage ◽  
Adaptive Biasing ◽  
Unity Gain ◽  
High Bandwidth ◽  
Cmos Amplifier

A low voltage low power two-stage CMOS amplifier with high open-loop gain, high gain bandwidth product (GBW) and enhanced slew rate is presented in this work. The proposed circuit makes use of folded cascode gm-boosting cells in conjunction with a low voltage gain enhanced cascode mirror using quasi-floating gate (QFGMOS) transistors. QFGMOS transistors are also used in input pair and adaptive biasing, which facilitate large dynamic output current in the presented circuit. Consequently, the slew rate is enhanced without much increase in static power dissipation. The unity gain frequency (UGF) and dc gain of the circuit are 29.4[Formula: see text]MHz and 132[Formula: see text]dB, respectively. The amplifier is operated at 0.6[Formula: see text]V dual supply with 89[Formula: see text][Formula: see text]W power consumption and has a nearly symmetrical average slew rate of 51.5[Formula: see text]V/[Formula: see text]s. All simulations including Monte Carlo and corner analysis are carried out using 180-nm CMOS technology for validating the design with help of spice tools.

Design Low Voltage FGMOS Operational Amplifier for Power Applications

2012 ◽  
Vol 433-440 ◽  
pp. 4189-4193 ◽  
Author(s):  
M. B. K. Jamal ◽  
S. P. Chew ◽  
B. I. Khadijah ◽  
S. B. M. Noormiza
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Electronic Device ◽  
Supply Voltage ◽  
High Gain ◽  
Battery Life ◽  
Op Amp ◽  
Integration Density ◽  
Low Power Dissipation ◽  
High Bandwidth

Due to the rise in demand for portable electronic device, low power and low voltage circuit design is extremely important for the appliances like computers, laptops, mobile phones and etc. Low power dissipation results in longer battery life and better integration density. This can be achieved by designing a modified low voltage op amp. The design of low voltage op amp in this paper is the combination of several low voltage analog cells. The modified low power op amp in this paper is built based on low voltage basic op amp. In this paper, the design objective is to achieve certain criteria such as supply voltage as low as 1 V, high gain more than 40 dB, low power consumption and high bandwidth. The use of FGMOS would increase the operating range of op amp through programming the threshold voltage of the FGMOS. This project is simulated using Silvaco Gateway and Expert.

Design of a Rail-to-Rail Operational Amplifier with Low Supply Voltage and Low Power Dissipation

2013 ◽  
Vol 380-384 ◽  
pp. 3275-3278
Author(s):  
Zhan Peng Jiang ◽  
Rui Xu ◽  
Hai Huang ◽  
Chang Chun Dong
Keyword(s):  
Power Dissipation ◽  
Operational Amplifier ◽  
Supply Voltage ◽  
High Gain ◽  
Op Amp ◽  
Rail To Rail ◽  
Dc Gain ◽  
Low Power Dissipation ◽  
Static Power ◽  
Low Supply Voltage

An rail-to-rail operational amplifier is presented in this paper, which is designed by with two op amp, the first level of the structure is the complementary differential structure which will providing input for the operational amplifier, the second level is designed with the structure of folding cascode to get a high gain. The operational amplifier is designed with the TSMC 0.35u m3.3VCMOS mixed analog-digital technology library. The simulated results show that the operational amplifier has a DC gain of 110dB,a GBW of 9.5MHz,a static power dissipation of 0.95mW,a phase margin of 73°,a voltage slew rate of 8.2V/μS,an input and output range of 0-3.3V,when operating at 3.3V power supply and a 20pF output load.

scholarly journals A 50.5 ns Wake-Up-Latency 11.2 pJ/Inst Asynchronous Wake-Up Controller in FDSOI 28 nm

2019 ◽  
Vol 9 (1) ◽  
pp. 8 ◽  
Author(s):  
Jean-Frédéric Christmann ◽  
Florent Berthier ◽  
David Coriat ◽  
Ivan Miro-Panades ◽  
Eric Guthmuller ◽  
...  
Keyword(s):  
Power Consumption ◽  
Supply Voltage ◽  
Silicon On Insulator ◽  
Instruction Set ◽  
Voltage Level ◽  
Fully Depleted ◽  
Environmental Variations ◽  
Reduced Instruction Set Computer ◽  
Low Activity ◽  
28 Nm

Due to low activity in Internet of Things (IoT) applications, systems tend to leverage low power modes in order to reduce their power consumption. Normally-off computing thus arose, consisting in having turned off most part of a system’s power supply, while dynamically turning on components as the application needs it. As wake up sources may be diverse, simple controllers are integrated to handle smart wake up schemes. Therefore, to prevent overconsumption while transitioning to running mode, fast wake up sequences are required. An asynchronous 16-bit Reduced Instruction Set Computer (RISC) Wake-up Controller (WuC) is proposed demonstrating 50.5 [email protected] Million Instructions Per Second (MIPS)@0.6 V wake-up latency, drastically reducing the overall wake-up energy of IoT systems. A clockless implementation of the controller saves the booting time and the power consumption of a clock generator, while providing high robustness to environmental variations such as supply voltage level. The WuC is also able to run simple tasks with a reduced Instruction Set Architecture (ISA) and achieves as low as 11.2 pJ/inst @0.5 V in Fully Depleted Silicon On Insulator (FDSOI) 28 nm.

scholarly journals Analysis of Charge Pump Topologies for High Voltage Mobile Microphone Applications

2021 ◽  
Vol 27 (2) ◽  
pp. 31-39
Author(s):  
Jakob K. Toft ◽  
Ivan H. H. Jorgensen
Keyword(s):  
Power Consumption ◽  
Mechanical System ◽  
High Voltage ◽  
Supply Voltage ◽  
Charge Pump ◽  
Micro Electro Mechanical System ◽  
Silicon On Insulator ◽  
High Bias ◽  
Low Supply Voltage ◽  
Very High

This paper presents a novel analysis of charge pump topologies for very high voltage capacitive drive micro electro-mechanical system microphones. For the application, the size and power consumption are sought to be minimized, and a voltage gain of 36 is achieved from a 5 V supply. The analysis compares known charge pump topologies, taking into consideration on resistance of transistors and parasitic capacitances of transistors and capacitors in a 180 nm silicon-on-insulator process. The analysis finds that the Pelliconi charge pump topology is optimal for generating very high bias voltages for micro electro-mechanical system microphones from a low supply voltage when the power consumption and area are limited by the application.

Sign in / Sign up

Export Citation Format

Share Document