scholarly journals Enhanced and Efficient Carry Select Adder with Minimal Delay

2021 ◽  
Author(s):  
G. Srividhya ◽  
T. Sivasakthi ◽  
R. Srivarshini ◽  
P. Varshaa ◽  
S. Vijayalakshmi
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Digital Signal ◽  
Propagation Delay ◽  
Digital Signal Processors ◽  
Digital World ◽  
Carry Select Adder ◽  
Image Processors ◽  
Improved Model ◽  
Signal Processors

In today’s digital world, Arithmetic computations have been evolved as a core factor in digital signal processors, micro-controllers, and systems using arithmetic and logical operations such as adders, multipliers, image processors, and signal processors. One of the elements that play an important role in performing arithmetic calculations is an adder. Among many adders, the Carry Select Adder produces less propagation delay. However, there may be an increased delay, power consumption, and area required in the case of a normal Carry Select Adder. To overcome the mentioned drawbacks, an improved model of Carry Select Adder has been designed that uses Binary to Excess – 1 Converter. Instead of using multiple blocks of Ripple Carry Adders (RCAs), it is efficient and effective if one of the blocks is replaced with Binary to Excess – 1 Converter. As a result, we can achieve a high speed adder with minimal delay, minimal power, and reduced area.

Simulation and Analysis of different CMOS Full Adders for Delay Optimisation

2021 ◽  
Vol 9 (9) ◽  
pp. 66-70
Author(s):  
Nakul C. Kubsad
Keyword(s):  
Power Dissipation ◽  
High Speed ◽  
Digital Signal ◽  
Full Adder ◽  
Digital Signal Processors ◽  
Transmission Gate ◽  
Logical Operations ◽  
Recent Advancement ◽  
Voltage Swing ◽  
Signal Processors

Abstract: Full adder circuit is one among the fundamental and necessary digital part. The full adder is be a part of microprocessors, digital signal processors etc. It's needed for the arithmetic and logical operations. Full adder design enhancements are necessary for recent advancement. The requirement of an adder cell is to provide high speed, consume low power and provide high voltage swing. This paper analyses and compares 3 adders with completely different logic designs (Conventional, transmission gate & pseudo NMOS) for transistor count, power dissipation and delay. The simulation is performed in Cadence virtuoso tool with accessible GPDK – 180nm kit. Transmission gate full adder has sheer advantage of high speed, fewer space and also it shows higher performance in terms of delay. Keywords: Delay, power dissipation, voltage, transistor sizing.

High Speed Vedic Multiplier for Digital Signal Processors

2009 ◽  
Vol 55 (6) ◽  
pp. 282 ◽  
Author(s):  
Ramesh Pushpangadan ◽  
Vineeth Sukumaran ◽  
Rino Innocent ◽  
Dinesh Sasikumar ◽  
Vaisak Sundar
Keyword(s):  
High Speed ◽  
Digital Signal ◽  
Digital Signal Processors ◽  
Vedic Multiplier ◽  
Signal Processors

scholarly journals High Speed, Low Area Exact Speculative Carry Look Ahead Adder using MGDI Technique

2019 ◽  
Vol 8 (6) ◽  
pp. 5090-5094
Keyword(s):  
Integrated Circuits ◽  
Power Consumption ◽  
High Speed ◽  
Digital Signal ◽  
Propagation Delay ◽  
Vital Role ◽  
Switching Behavior ◽  
Low Area ◽  
Look Ahead ◽  
Heating Up

The Exact Speculative Carry Look Ahead Adder using the Modified-GDI (Modified-Gate Diffusion Input) is suggested in this work. The delay, area and power tradeoff plays a vital role in VLSI. We already know that designs which are of CMOS style occupy more space may consume more power consumption. The switching behavior of the circuit cause the heating up of integrated circuits affects the working conditions of the functional unit. The adders are the main parts of several applications such as microprocessors, microcontrollers and digital signal processors and also in real time applications. Hence it is important to minimize the adder blocks to design a perfect processor. This work is proposed on a 16 bit carry look ahead adder is designed by using MGDI gate and 4T XOR gates and a speculator blocks. The proposed MGDI carry Look Ahead adder occupies 68% less area and the power consumption and the propagation delay also drastically reduces when compared to the conventional carry Look Ahead adder why because the number transistors drastically reduces from 1448 (Conventional) to 456 (Proposed CLA). The simulation results of the proposed design implemented in Xilinx.

scholarly journals FPGA Based Vector Control of Induction Motor

2020 ◽  
Vol 9 (4) ◽  
pp. 572-577
Keyword(s):  
Induction Motor ◽  
High Speed ◽  
Digital Signal ◽  
Digital Signal Processors ◽  
Electronic Industry ◽  
New Approach ◽  
The Past ◽  
Field Programmable ◽  
Signal Processors ◽  
Very High

To get the desired response of the sensor less Vector controlled Induction Motor (SVC-IM) by the experimental setup, the controller implementation for the generation of the PWM signals is the key role. It is possible with the rapid growth of electronic industry such as high speed digital signal processors (DSPs) with micro controllers available in the present market. In the past DSP technologies were used to realize the several SVC-IM schemes, i.e. KF, PI, GA and PSO respectively. However, it creates issues related to the time delay and execution of the PWM signals, etc., as a results system becomes complex. Therefore a new approach is implemented to overcome the issues related to the execution time, namely Field Programmable Gate Array (FPGA) processors are suggested in the present market. Moreover the programming is done using very high speed hardware descriptive language (VHDL)

scholarly journals A Comparative Review on ALU using CMOS and GDI techniques for Power Dissipation and Propagation Delay

IJOSTHE ◽  
2020 ◽  
Vol 7 (1) ◽  
pp. 4
Author(s):  
Rimjhim Saxena ◽  
Kiran Sharma
Keyword(s):  
Power Consumption ◽  
Power Dissipation ◽  
High Speed ◽  
Digital Signal ◽  
Propagation Delay ◽  
Logic Circuits ◽  
Compact Size ◽  
Comparative Review ◽  
Basic Functions ◽  
The One

Arithmetic and Logic Circuits are to be designed with less power, compact size, less propagation delay in this fast growing era of technology. Arithmetic operations are indispensable and the basic functions for any high speed low power applications like digital signal processing, microprocessors, image processing, etc. Consumption of power is the major issue in designing these circuits. Also the number of transistors required is also the one of the issues in designing the circuits. To minimize the transistors required in designing the circuits and to reduce the power consumption of the circuits, the authors have referred some techniques to overcome these problems in this paper. By reviewing all these techniques, the authors try to implement the GDI technique to reduce the power consumption and transistors count or the area required to design the circuits.

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