Hardware implementation of an α - level based binary search and shifting fuzzifier (α - BSSF)

2020 ◽  
Vol 39 (5) ◽  
pp. 6671-6685
Author(s):  
César Barrón-Romero ◽  
Antonio Hernández-Zavala
Keyword(s):  
Low Cost ◽  
Mechatronic Systems ◽  
Gate Arrays ◽  
High Processing Speed ◽  
Short Development Time ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Design Characteristics ◽  
Α Level ◽  
Computational Resources

Fuzzy processors are used for control actions in nonlinear mechatronic systems where high processing speed is required. The Field Programmable Gate Arrays (FPGA) are a good option to implement low cost fuzzy hardware in a short development time. A very important block in fuzzy hardware is the fuzzifier, since it affects directly in the accuracy of the result and in the processing time for obtaining a fuzzy number. There have been many design methodologies intended for enhancing the performance of this block. This paper presents a parallel fuzzifier circuit called α-BSSF. Its main design characteristics are the use of α-levels for membership representation, usage of integer numbers, and avoiding time-consuming operations. As result, we obtained a fuzzifier that shows advantages in the reduction of the response time and computational resources against the existing sequential fuzzification methods. This proposal is targeted not only for T1FS, but also for T2FS, since the membership calculation through fuzzifier is applied in the same way but twice.

High Performance Low Cost Implementation of FPGA-Based Fractional-Order Operators

2005 ◽  
Author(s):  
Cindy X. Jiang ◽  
Tom T. Hartley ◽  
Joan E. Carletta
Keyword(s):  
Fractional Order ◽  
Word Length ◽  
High Performance ◽  
Low Cost ◽  
Careful Consideration ◽  
Order System ◽  
System Quality ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays

Hardware implementation of fractional-order differentiators and integrators requires careful consideration of issues of system quality, hardware cost, and speed. This paper proposes using field programmable gate arrays (FPGAs) to implement fractional-order systems, and demonstrates the advantages that FPGAs provide. As an illustration, the fundamental operators to a real power is approximated via the binomial expansion of the backward difference. The resulting high-order FIR filter is implemented in a pipelined multiplierless architecture on a low-cost Spartan-3 FPGA. Unlike common digital implementations in which all filter coefficients have the same word length, this approach exploits variable word length for each coefficient. Our system requires twenty percent less hardware than a system of comparable quality generated by Xilinx’s System Generator on its most area-efficient multiplierless setting. The work shows an effective way to implement a high quality, high throughput approximation to a fractional-order system, while maintaining less cost than traditional FPGA-based designs.

scholarly journals A High Resolution Vernier Digital-to-Time Converter Implemented with 65 nm FPGA

2019 ◽  
Vol 9 (13) ◽  
pp. 2705
Author(s):  
Chenggang Yan ◽  
Chen Hu ◽  
Jianhui Wu
Keyword(s):  
High Resolution ◽  
Low Cost ◽  
Phase Locked Loops ◽  
Least Significant Bit ◽  
Gate Arrays ◽  
Differential Nonlinearity ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Fpga Chip ◽  
Fine Resolution

In this paper, a digital-to-time converter (DTC) based on the three delay lines (3D) Vernier principle is proposed and implemented with field programmable gate arrays (FPGAs). Based on the 3D Vernier principle, the DTC is realized by three period approximate phase locked loops (PLLs). The theoretical fine resolution of the proposed DTC is improved by calculating the period difference two times. The achieved resolution of the proposed DTC is 203 fs realized with an Altera Stratix III FPGA chip, which is about tenfold higher than traditional FPGA-DTC implemented with the same series FPGAs. The worst absolute differential nonlinearity (DNL) and integral nonlinearity (INL) are verified smaller than 0.88 least significant bit (LSB) and 4.4 LSB, respectively. By optimized computation logic, there are only 448 adaptive look-up-tables (ALUTs), 237 registers and three phase locked loops (PLLs) utilized for circuit implementation. Experimental results prove that the proposed DTC features high resolution with low cost.

FPGA TECHNOLOGY IN PROCESS TOMOGRAPHY

2016 ◽  
Vol 78 (7-4) ◽  
Author(s):  
Lean Thiam Siow ◽  
Mohd Hafiz Fazalul Rahiman ◽  
Ruzairi Abdul Rahim ◽  
Mohd Shukry Abdul Majid ◽  
Salman Sayyidi Hamzah ◽  
...  
Keyword(s):  
High Speed ◽  
Low Cost ◽  
Gate Arrays ◽  
Tomography System ◽  
Process Tomography ◽  
Ultrasonic Process ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Future Work

The aims of this paper are to provide a review of the process tomography applications employing field programmable gate arrays (FPGA) and to understand current FPGA related researches, in order to seek for the possibility to applied FPGA technology in an ultrasonic process tomography system. FPGA allows users to implement complete systems on a programmable chip, meanwhile, five main benefits of applying the FPGA technology are performance, time to market, cost, reliability, and long-term maintenance. These advantages definitely could help in the revolution of process tomography, especially for ultrasonic process tomography and electrical process tomography. Future work is focused on the ultrasonic process tomography for chemical process column investigation using FPGA for the aspects of low cost, high speed and reconstructed image quality.

scholarly journals Evaluation of the Different Numerical Formats for HIL Models of Power Converters after the Adoption of VHDL-2008 by Xilinx

Electronics ◽  
2021 ◽  
Vol 10 (16) ◽  
pp. 1952
Author(s):  
Eva M. Cirugeda-Roldán ◽  
María Sofía Martínez-García ◽  
Alberto Sanchez ◽  
Angel de Castro
Keyword(s):  
High Speed ◽  
Power Converters ◽  
Low Cost ◽  
Hardware In The Loop ◽  
Main Design ◽  
Gate Arrays ◽  
The World ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Area Optimization

Hardware in the loop is a widely used technique in power electronics, allowing to test and debug in real time (RT) at a low cost. In this context, field-programmable gate arrays (FPGAs) play an important role due to the high-speed requirements of RT simulations, in which area optimization is also crucial. Both characteristics, area and speed, are affected by the numerical formats (NFs) and their rounding modes. Regarding FPGAs, Xilinx is one of the largest manufacturers in the world, offering Vivado as its main design suite, but it was not until the release of Vivado 2020.2 that support for the IEEE NF libraries of VHDL-2008 was included. This work presents an exhaustive evaluation of the performance of Vivado 2020.2 in terms of area and speed using the native IEEE libraries of VHDL-2008 regarding NF. Results show that even though fixed-point NFs optimize area and speed, if a user prefers the use of floating-point NFs, with this new release, it can be synthesized—which could not be done in previous versions of Vivado. Although support for the native IEEE libraries of VHDL-2008 was included in Vivado 2020.2, it still lacks some issues regarding NF conversion during synthesis while support for simulation is not yet included.

scholarly journals The Use of Field-Programmable Gate Arrays for the Hardware Acceleration of Design Automation Tasks

VLSI Design ◽  
1996 ◽  
Vol 4 (2) ◽  
pp. 135-139 ◽  
Author(s):  
Neil J. Howard ◽  
Andrew M. Tyrrell ◽  
Nigel M. Allinson
Keyword(s):  
Design Process ◽  
Low Cost ◽  
Vlsi Design ◽  
Hardware Acceleration ◽  
Field Programmable Gate Arrays ◽  
Design Rule ◽  
Gate Arrays ◽  
Field Programmable ◽  
Design Rule Checking ◽  
Programmable Gate Arrays

This paper investigates the possibility of using Field-Programmable Gate Arrays (Fpgas) as reconfigurable co-processors for workstations to produce moderate speedups for most tasks in the design process, resulting in a worthwhile overall design process speedup at low cost and allowing algorithm upgrades with no hardware modification. The use of Fpgas as hardware accelerators is reviewed and then achievable speedups are predicted for logic simulation and VLSI design rule checking tasks for various Fpga co-processor arrangements.

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