scholarly journals Audio, Image, Video, and Weather Datasets for Continuous Electronic Beehive Monitoring

2021 ◽  
Vol 11 (10) ◽  
pp. 4632
Author(s):  
Vladimir Kulyukin

In 2014, we designed and implemented BeePi, a multi-sensor electronic beehive monitoring system. Since then we have been using BeePi monitors deployed at different apiaries in northern Utah to design audio, image, and video processing algorithms to analyze forager traffic in the vicinity of Langstroth beehives. Since our first publication on BeePi in 2016, we have received multiple requests from researchers and practitioners for the datasets we have used in our research. The main objective of this article is to provide a comprehensive point of reference to the datasets that we have so far curated for our research. We hope that our datasets will provide stable performance benchmarks for continuous electronic beehive monitoring, help interested parties verify our findings and correct errors, and advance the state of the art in continuous electronic beehive monitoring and related areas of AI, machine learning, and data science.

The emphasis on analysis of various research schemes of non – intrusive software based face spoofing detection is now a days gaining reputation in image and video processing tools. The analysis on luminance(Y)data of the various face images which provides the discrimination of forged faces from genuine faces by removing the chroma component. Here the work provides an innovative approach that perceives spoofed face using texture analysis (colour)by exploiting combined colour texture information from various channels such as luminance and chrominance. This helps to exploit joint information by removing degraded feature metaphors from dissimilar colour models.Precisely the featured histograms are figured over all images that obtained from the YCrCb colour model band distinctly.The concatenation of testing and training by using Neural Network for classification of spoofed images by the concept of blending of images gives the best possible outcomes. Wide-ranging researches on face data bases is most interesting target datasets paves the way for best processing face spoofing results than state of art. The proposed method gives stable performance when compared with the most unlike methods that conferred in the literature survey. The promising outcomes of evaluation suggests that facial colour texture depiction is added steady strange conditions associated to gray-scale complements.The favourableoutcomeswereattained using these CNN(Convolution Neural Network)designs for face antispoofing in diversesituations.


Author(s):  
Murad Qasaimeh ◽  
Ehab Najeh Salahat

Implementing high-performance, low-cost hardware accelerators for the computationally intensive image and video processing algorithms has attracted a lot of attention in the last 20 years. Most of the recent research efforts were trying to figure out new design automation methods to fill the gap between the ability of realizing efficient accelerators in hardware and the tight performance requirements of the complex image processing algorithms. High-Level synthesis (HLS) is a new method to automate the design process by transforming high-level algorithmic description into digital hardware while satisfying the design constraints. This chapter focuses on evaluating the suitability of using HLS as a new tool to accelerate the most demanding image and video processing algorithms in hardware. It discusses the gained benefits and current limitations, the recent academic and commercial tools, the compiler's optimization techniques and four case studies.


2018 ◽  
pp. 1004-1022
Author(s):  
Murad Qasaimeh ◽  
Ehab Najeh Salahat

Implementing high-performance, low-cost hardware accelerators for the computationally intensive image and video processing algorithms has attracted a lot of attention in the last 20 years. Most of the recent research efforts were trying to figure out new design automation methods to fill the gap between the ability of realizing efficient accelerators in hardware and the tight performance requirements of the complex image processing algorithms. High-Level synthesis (HLS) is a new method to automate the design process by transforming high-level algorithmic description into digital hardware while satisfying the design constraints. This chapter focuses on evaluating the suitability of using HLS as a new tool to accelerate the most demanding image and video processing algorithms in hardware. It discusses the gained benefits and current limitations, the recent academic and commercial tools, the compiler's optimization techniques and four case studies.


2018 ◽  
Vol 1 (2) ◽  
pp. 17-23
Author(s):  
Takialddin Al Smadi

This survey outlines the use of computer vision in Image and video processing in multidisciplinary applications; either in academia or industry, which are active in this field.The scope of this paper covers the theoretical and practical aspects in image and video processing in addition of computer vision, from essential research to evolution of application.In this paper a various subjects of image processing and computer vision will be demonstrated ,these subjects are spanned from the evolution of mobile augmented reality (MAR) applications, to augmented reality under 3D modeling and real time depth imaging, video processing algorithms will be discussed to get higher depth video compression, beside that in the field of mobile platform an automatic computer vision system for citrus fruit has been implemented ,where the Bayesian classification with Boundary Growing to detect the text in the video scene. Also the paper illustrates the usability of the handed interactive method to the portable projector based on augmented reality.   © 2018 JASET, International Scholars and Researchers Association


2020 ◽  
Author(s):  
Saeed Nosratabadi ◽  
Amir Mosavi ◽  
Puhong Duan ◽  
Pedram Ghamisi ◽  
Ferdinand Filip ◽  
...  

This paper provides a state-of-the-art investigation of advances in data science in emerging economic applications. The analysis was performed on novel data science methods in four individual classes of deep learning models, hybrid deep learning models, hybrid machine learning, and ensemble models. Application domains include a wide and diverse range of economics research from the stock market, marketing, and e-commerce to corporate banking and cryptocurrency. Prisma method, a systematic literature review methodology, was used to ensure the quality of the survey. The findings reveal that the trends follow the advancement of hybrid models, which, based on the accuracy metric, outperform other learning algorithms. It is further expected that the trends will converge toward the advancements of sophisticated hybrid deep learning models.


Author(s):  
Chamin Morikawa ◽  
Michihiro Kobayashi ◽  
Masaki Satoh ◽  
Yasuhiro Kuroda ◽  
Teppei Inomata ◽  
...  

2016 ◽  
Vol 26 (04) ◽  
pp. 1750054
Author(s):  
M. Kiruba ◽  
V. Sumathy

The Discrete Cosine Transform (DCT) structure plays a significant role in the signal processing applications such as image and video processing applications. In the traditional hardware design, the 8-point DCT architecture contains more number of logical slices in it. Also, it consists of number of multipliers to update the weight. This leads to huge area consumption and power dissipation in that architecture. To mitigate the conventional drawbacks, this paper presents a novel Hierarchical-based Expression (HBE)-Multiple Constant Multiplication (MCM)-based multiplier architecture design for the 8-point DCT structure used in the video CODEC applications. The proposed work involves modified data path architecture and Floating Point Processing Element (FPPE) architecture. Our proposed design of the multipliers and DCT architecture requires minimum number of components when compared to the traditional DCT method. The HBE-MCM-based multiplier architecture includes shifters and adders. The number of Flip-Flops (FFs) and Look Up Tables (LUTs) used in the proposed architecture is reduced. The power consumption is reduced due to the reduction in the size of the components. This design is synthesized in VERILOG code language and implemented in the Field Programmable Gate Array (FPGA). The performance of the proposed architecture is evaluated by comparing it with traditional DCT architecture in terms of the Number of FFs, Number of LUTs, area, power, delay and speed.


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