scholarly journals Design and Implementation of New Coplanar FA Circuits without NOT Gate and Based on Quantum-Dot Cellular Automata Technology

2021 ◽  
Vol 11 (24) ◽  
pp. 12157
Author(s):  
Mohsen Vahabi ◽  
Pavel Lyakhov ◽  
Ali Newaz Bahar ◽  
Khan A. Wahid
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Logic Gate ◽  
Logic Gates ◽  
Full Adder ◽  
Cmos Technology ◽  
Ultra Low Power ◽  
Xor Gate ◽  
Design Complexity ◽  
Quantum Dot Cellular Automata

The miniaturization of electronic devices and the inefficiency of CMOS technology due to the development of integrated circuits and its lack of responsiveness at the nanoscale have led to the acquisition of nanoscale technologies. Among these technologies, quantum-dot cellular automata (QCA) is considered one of the possible replacements for CMOS technology because of its extraordinary advantages, such as higher speed, smaller area, and ultra-low power consumption. In arithmetic and comparative circuits, XOR logic is widely used. The construction of arithmetic logic circuits using AND, OR, and NOT logic gates has a higher design complexity. However, XOR gate design has a lower design complexity. Hence, the efficient and optimized XOR logic gate is very important. In this article, we proposed a new XOR gate based on cell-level methodology, with the expected output achieved by the influence of the cells on each other; this design method caused less delay. However, this design was implemented without the use of inverter gates and crossovers, as well as rotating cells. Using the proposed XOR gate, two new full adder (FA) circuits were designed. The simulation results indicate the advantage of the proposed designs compared with previous structures.

scholarly journals Design of Efficient Full Adder in Quantum-Dot Cellular Automata

2013 ◽  
Vol 2013 ◽  
pp. 1-10 ◽  
Author(s):  
Bibhash Sen ◽  
Ayush Rajoria ◽  
Biplab K. Sikdar
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Full Adder ◽  
Cmos Technology ◽  
Digital Design ◽  
Majority Gate ◽  
Feature Size ◽  
Quantum Dot Cellular Automata ◽  
Potential Alternative ◽  
High Level

Further downscaling of CMOS technology becomes challenging as it faces limitation of feature size reduction. Quantum-dot cellular automata (QCA), a potential alternative to CMOS, promises efficient digital design at nanoscale. Investigations on the reduction of QCA primitives (majority gates and inverters) for various adders are limited, and very few designs exist for reference. As a result, design of adders under QCA framework is gaining its importance in recent research. This work targets developing multi-layered full adder architecture in QCA framework based on five-input majority gate proposed here. A minimum clock zone (2 clock) with high compaction (0.01 μm2) for a full adder around QCA is achieved. Further, the usefulness of such design is established with the synthesis of high-level logic. Experimental results illustrate the significant improvements in design level in terms of circuit area, cell count, and clock compared to that of conventional design approaches.

Design of quantum dot cellular automata based fault tolerant convolution encoders for secure nanocomputing

2020 ◽  
Vol 18 (06) ◽  
pp. 2050032
Author(s):  
Suhaib Ahmed ◽  
Syed Farah Naz
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Communication Networks ◽  
Data Transfer ◽  
Fault Tolerant ◽  
Satellite Communications ◽  
Cmos Technology ◽  
Ultra Low Power ◽  
Quantum Dot Cellular Automata ◽  
Cost Efficient

The issues faced by Complementary metal oxide semi-conductor (CMOS) technology in the nanoregime have led to the research of other possible technologies which can operate with same functionalities however, with higher speed and lower power dissipation. One such technology is Quantum-dot Cellular Automata (QCA). At present, logic circuit designs using QCA have been comprehensively researched and one such application area being investigated is data transmission. Various data transfer techniques for reliable data transfer are available and among them convolution coding is being widely used in mobile, radio and satellite communications. Considering the evolution towards nano communication networks, in this paper an ultra-proficient designs of 1/2 rate and 1/3 rate convolution encoders based on a cost-efficient and fault tolerant XOR gate design have been proposed for application in nano communication networks. Based on the performance analysis, it is observed that the proposed designs are efficient in respect to cell count, area, delay and circuit cost and achieves performance improvement up to 40.21% for 1/2 encoder and 31.81% for 1/3 encoder compared to the best design in the literature. In addition to this, the energy dissipation analysis of the proposed designs is also presented. The proposed designs can thus be efficiently utilized in various nanocommunication applications requiring minimal area and ultra-low power consumption.

scholarly journals Design and Implementation of Programmable Logic Array Using Quantum Dot Cellular Automata

2020 ◽  
Vol 5 (3) ◽  
pp. 01-08
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Logic Gates ◽  
Cmos Technology ◽  
Programmable Logic ◽  
Quantum Dot Cellular Automata ◽  
Design And Implementation ◽  
Programmable Logic Array ◽  
Logic Array ◽  
Theoretical Results

Quantum Dot Cellular Automata (QCA) is an alternative to CMOS technology. The other technologies proposed by researchers are FINFET, CNTs and MTJ to reduce scalability of CMOS devices. Using Quantum Dot Cellular Automata, the low power, extremely dense circuits are designed. QCA cell is the fundamental unit in building logic gates. These cells are powered using specific clock. QCA cells are used to design basic gates and to realize Boolean expressions. QCA Designer tool is used to carry out simulations. The simulation results are same as theoretical results. The complexity and size of circuits are reduced using QCA. The paper includes design of Programmable Logic Array (PLA).

scholarly journals Design and Implementation of Novel Efficient Full Adder/Subtractor Circuits Based on Quantum-Dot Cellular Automata Technology

2021 ◽  
Vol 11 (18) ◽  
pp. 8717
Author(s):  
Mohsen Vahabi ◽  
Pavel Lyakhov ◽  
Ali Newaz Bahar
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
High Speed ◽  
Single Layer ◽  
Building Blocks ◽  
Full Adder ◽  
Cmos Technology ◽  
Quantum Dot Cellular Automata ◽  
Potential Alternative ◽  
Nanoscale Level

One of the emerging technologies at the nanoscale level is the Quantum-Dot Cellular Automata (QCA) technology, which is a potential alternative to conventional CMOS technology due to its high speed, low power consumption, low latency, and possible implementation at the atomic and molecular levels. Adders are one of the most basic digital computing circuits and one of the main building blocks of VLSI systems, such as various microprocessors and processors. Many research studies have been focusing on computable digital computing circuits. The design of a Full Adder/Subtractor (FA/S), a composite and computing circuit, performing both the addition and the subtraction processes, is of particular importance. This paper implements three new Full Adder/Subtractor circuits with the lowest number of cells, lowest area, lowest latency, and a coplanar (single-layer) circuit design, as was shown by comparing the results obtained with those of the best previous works on this topic.

Towards the Design of Cost-efficient Generic Register Using Quantum-dot Cellular Automata

2020 ◽  
Vol 10 (4) ◽  
pp. 534-547
Author(s):  
Chiradeep Mukherjee ◽  
Saradindu Panda ◽  
Asish K. Mukhopadhyay ◽  
Bansibadan Maji
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Power Dissipation ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Digital Data ◽  
Design Parameters ◽  
Flip Flop ◽  
Quantum Dot Cellular Automata ◽  
Cost Efficient

Background: The advancement of VLSI in the application of emerging nanotechnology explores quantum-dot cellular automata (QCA) which has got wide acceptance owing to its ultra-high operating speed, extremely low power dissipation with a considerable reduction in feature size. The QCA architectures are emerging as a potential alternative to the conventional complementary metal oxide semiconductor (CMOS) technology. Experimental: Since the register unit has a crucial role in digital data transfer between the electronic devices, such study leading to the design of cost-efficient and highly reliable QCA register is expected to be a prudent area of research. A thorough survey on the existing literature shows that the generic models of Serial-in Serial Out (SISO), Serial-in-Parallel-Out (SIPO), Parallel-In- Serial-Out (PISO) and Parallel-in-Parallel-Out (PIPO) registers are inadequate in terms of design parameters like effective area, delay, O-Cost, Costα, etc. Results: This work introduces a layered T gate for the design of the D flip flop (LTD unit), which can be broadly used in SISO, SIPO, PISO, and PIPO register designs. For detection and reporting of high susceptible errors and defects at the nanoscale, the reliability and defect tolerant analysis of LTD unit are also carried out in this work. The QCA design metrics for the general register layouts using LTD unit is modeled. Conclusion: Moreover, the cost metrics for the proposed LTD layouts are thoroughly studied to check the functional complexity, fabrication difficulty and irreversible power dissipation of QCA register layouts.

Design of Efficient and Testable n-Input Logic Gates in Quantum-Dot Cellular Automata

2013 ◽  
Vol 10 (10) ◽  
pp. 2347-2353 ◽  
Author(s):  
Samira Sayedsalehi ◽  
Mohammad Hossein Moaiyeri ◽  
Keivan Navi
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Logic Gates ◽  
Quantum Dot Cellular Automata
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