scholarly journals FPGA-Implemented Fractal Decoder with Forward Error Correction in Short-Reach Optical Interconnects

Entropy ◽  
2022 ◽  
Vol 24 (1) ◽  
pp. 122
Author(s):  
Svitlana Matsenko ◽  
Oleksiy Borysenko ◽  
Sandis Spolitis ◽  
Aleksejs Udalcovs ◽  
Lilita Gegere ◽  
...  
Keyword(s):  
Error Correction ◽  
Error Detection ◽  
Optical Interconnects ◽  
Error Control ◽  
Forward Error Correction ◽  
Golden Ratio ◽  
Probability Method ◽  
Additional Error ◽  
Hardware Costs ◽  
Forward Error

Forward error correction (FEC) codes combined with high-order modulator formats, i.e., coded modulation (CM), are essential in optical communication networks to achieve highly efficient and reliable communication. The task of providing additional error control in the design of CM systems with high-performance requirements remains urgent. As an additional control of CM systems, we propose to use indivisible error detection codes based on a positional number system. In this work, we evaluated the indivisible code using the average probability method (APM) for the binary symmetric channel (BSC), which has the simplicity, versatility and reliability of the estimate, which is close to reality. The APM allows for evaluation and compares indivisible codes according to parameters of correct transmission, and detectable and undetectable errors. Indivisible codes allow for the end-to-end (E2E) control of the transmission and processing of information in digital systems and design devices with a regular structure and high speed. This study researched a fractal decoder device for additional error control, implemented in field-programmable gate array (FPGA) software with FEC for short-reach optical interconnects with multilevel pulse amplitude (PAM-M) modulated with Gray code mapping. Indivisible codes with natural redundancy require far fewer hardware costs to develop and implement encoding and decoding devices with a sufficiently high error detection efficiency. We achieved a reduction in hardware costs for a fractal decoder by using the fractal property of the indivisible code from 10% to 30% for different n while receiving the reciprocal of the golden ratio.

Forward Error Correction by Means of Microprocessors

1980 ◽  
Vol 17 (1) ◽  
pp. 67-75
Author(s):  
D. H. Green ◽  
A. P. Ambler
Keyword(s):  
Error Correction ◽  
Error Control ◽  
Forward Error Correction ◽  
Error Control Coding ◽  
Coding Schemes ◽  
Data Rates ◽  
Forward Error

The feasibility of employing a microprocessor to perform the various tasks involved with the implementation of a number of well known error-control coding schemes is investigated. It is demonstrated that reasonable data-rates can be achieved with even quite powerful codes.

scholarly journals Forward Error Correction Using Turbo Codes for Multimedia Data

2018 ◽  
pp. 1-7
Author(s):  
M. Subramanya ◽  
Shaiesta Khuteja ◽  
K. C. Varun Kumar ◽  
S. Srilatha ◽  
B. V. Srividya
Keyword(s):  
Error Correction ◽  
Turbo Codes ◽  
Error Control ◽  
Forward Error Correction ◽  
Turbo Code ◽  
Error Rates ◽  
Multimedia Data ◽  
Channel Fading ◽  
Physical Channel ◽  
Forward Error

The swift growth in multimedia technology of wireless network has made it mandatory for the efficient transmission across erratic channel. The transmission of encoded video using error control techniques is grabbing a great attention, since it works over the recovery of the lost data and errors in the bit frames which occur as a result of congestion and physical channel fading. Turbo codes are attracting researchers because of their efficient performance. The Turbo code is made up of analogous concatenation of two Recursive Systematic Convolutional (RSC) coders parted by a  non-uniform interleaver. For different code rate and information block lengths greater than 104, these codes are capable of achieving low Bit-error rates (BERs) at SNRs within 1dB of Shannon’s limit. Turbo codes will assist to employ Viterbi decoders. More the number of iterations, higher is the error correction capacity and hence Turbo codes act as an elucidation for obtaining large coding gains.

ANALISIS KEADILAN MODEL PENJADWALAN YANG DIINTEGRASIKAN DENGAN HARQ PADA SISTEM LTE

2016 ◽  
Vol 1 (1) ◽  
Author(s):  
Danu Dwi Sanjoyo ◽  
Rendy Munadi ◽  
Ida Wahidah
Keyword(s):  
Error Correction ◽  
Error Detection ◽  
Forward Error Correction ◽  
Proportional Fairness ◽  
Quality Information ◽  
Channel Quality ◽  
Term Evolution ◽  
Forward Error ◽  
Channel Quality Information

Penjadwalan pada Long Term Evolution (LTE) memiliki peran dalam melayani kebutuhan bandwidth yang besar. Oleh karena itu, jaringan seluler LTE membutuhkan algoritma penjadwalan yang mampu mengakomodasi informasi keluaran dari proses HARQ untuk meningkatkan fairness. Algoritma penjadwalan dikombinasikan dengan proses HARQ untuk meningkatkan keadilan throughput yang diterima oleh pengguna. Redundancy Version (RV) yang diperoleh dari proses HARQ dikombinasikan dengan nilai prioritas layanan dan Channel Quality Information (CQI) menjadi suatu nilai metrik yang digunakan untuk menentukan prioritas paket pada proses penjadwalan. Algoritma penjadwalan diujikan pada makalah ini adalah Round Robin (RR), Maximum C/I (CI), dan Proportional Fairness (PF). Proses HARQ di penerima melakukan Error Detection (ED) dan Forward Error Correction (FEC) pada paket yang diterima. User Equipment (UE) akan mengirimkan feedback ke eNode-B yang berisi informasi apakah paket berhasil diterima dengan benar atau tidak. Integrasi masing-masing algoritma penjadwalan (RR, CI, dan PF) dengan nilai CQI, rangking paket data, dan RV dapat meningkatkan nilai fairness antarpengguna. Jain�s Fairnees Index, sebagai parameter keadilan, menunjukkan adanya peningkatan keadilan throughput.Kata kunci: LTE, penjadwalan, HARQ, Jain�s Fairness Index

scholarly journals Proposed Method to Generated Strong Keys by Fuzzy Extractor And Biometric

2018 ◽  
Vol 7 (3.27) ◽  
pp. 129 ◽  
Author(s):  
Huda Saleem ◽  
Huda Albermany ◽  
Husein Hadi
Keyword(s):  
Error Correction ◽  
Error Control ◽  
Forward Error Correction ◽  
Error Correcting Codes ◽  
Fuzzy Extractor ◽  
Biometric Data ◽  
Convolutional Coding ◽  
Noise Data ◽  
Typical Scheme ◽  
Forward Error

The typical scheme used to generated cryptographic key is a fuzzy extractor. The fuzzy extractor is the extraction of a stable data from biometric data or noisy data based on the error correction code (ECC) method. Forward error correction includes two ways are blocked and convolutional coding used for error control coding. “Bose_Chaudhuri_Hocquenghem” (BCH) is one of the error correcting codes employ to correct errors in noise data. In this paper use fuzzy extractor scheme to find strong key based on BCH coding, face recognition data used SVD method and hash function. Hash_512 converted a string with variable length into a string of fixed length, it aims to protect information against the threat of repudiation.  

scholarly journals Designing VHDL to Simulate the Error Correction of Hamming Code

2018 ◽  
Vol 1 (2) ◽  
Author(s):  
A. Mahmudi ◽  
S. Achmadi
Keyword(s):  
Error Correction ◽  
Error Detection ◽  
Forward Error Correction ◽  
Data Communication ◽  
Hamming Code ◽  
Data Errors ◽  
Quasi Experimental ◽  
Forward Error ◽  
Correct Data

The role of error detection and error correction for the data bit by the receiver is very important because the sender does not need to repeat the transmissions. Thus, the speed and reliability in transmitting data information can be maintained. This study aims to implement simulation the Forward Error Correction (FEC) method in verifying and correcting data errors received by using simulation. To support FEC method, study utilizes visual basic software so that it can be used as one of the quasi-experimental modules in the data communication laboratory. The Forward Error Correction (FEC) method is a method that can correct data errors in the receiver. This method uses simulated Hamming codes on the computer so that the detection and correction process can be clearly demonstrated on the monitor screen. This simulation can be used as a quasi-experimental module in a data communication laboratory. The simulation results show that the Hamming code (17, 12) codec has been running as expected.

scholarly journals SIMULASI KINERJA FORWARD ERROR CONTROL CODING UNTUK SATELIT MIKRO PENGINDERAAN JARAK JAUH

2012 ◽  
Vol 9 (2) ◽  
Author(s):  
Dwiyanto ◽  
Sugihartono
Keyword(s):  
Remote Sensing ◽  
Error Correction ◽  
Error Control ◽  
Forward Error Correction ◽  
Satellite Communication ◽  
Correction Method ◽  
Error Control Coding ◽  
Simulation Performance ◽  
Forward Error Control ◽  
Forward Error

Micro satellite application for remote sensing in this time has been expanded and particularly supported by growth of electronics component that low power and small size. Large amount of image data, less of contact time and limited satellite’s power obliges of efficiency mechanism design to assured data satellite communication is accepted properly by earth station. Various of scenario of data transmissions on micro satellite have been developed in order to ensure all data that taken by payload can be delivered and accepted by station earth truly. Forward Error Control Coding or Forward Error Correction method is mechanism that added redundancy bit to delivery data with a purpose to improve error correction of received data. FEC performance can be known by compare of different value of Eb/N0 needed for Bit Error Rate (BER) in common without FEC. In this research conducted simulation performance FEC Reed Solomon by undertaking change of beet amount per symbol, code length and code ability in repairing symbol error. Simulation Result shows getting smaller code rate that used then ever greater code reinforcement. The simulation using forward error control coding Reed Solomon for data transmission remote sensing results code RS(255,223) have best performance with coderate 0,874 and coding gain 3,4dB on value of BER 10-4. Keywords: Reed Solomon, QPSK, 16-QAM, Remote sensing

scholarly journals Literature Review on High Definition Image Error Concealment

2018 ◽  
Vol 7 (3.12) ◽  
pp. 165
Author(s):  
Ghouse Ahamed Z ◽  
Anuj Jain
Keyword(s):  
Error Correction ◽  
Error Detection ◽  
Error Control ◽  
Forward Error Correction ◽  
Error Concealment ◽  
Control Method ◽  
Error Resilience ◽  
Control Mechanisms ◽  
High Definition ◽  
Error Control Mechanism

This paper is give us a overview of Error control method used in image or video transmission. Data in transmission is lost due to link failure or due to congestion and loss in packets, so the aim of this method is to protect data from these errors. Error detection coding and Error correction coding are two types of error control mechanism. Some of the error control mechanisms are Retransmission, Forward error correction, error concealment and error resilience. We are discussing a summary of three methods and Error Concealment in details.  

scholarly journals FPGA Implementation of UART with Single Error Correction and Double Error Detection (UART-SEC-DED)

2018 ◽  
Vol 7 (3.12) ◽  
pp. 23
Author(s):  
Amrutha Gorabal ◽  
Nayana D K
Keyword(s):  
Error Correction ◽  
Error Detection ◽  
Forward Error Correction ◽  
Communication Protocol ◽  
Full Duplex ◽  
Module Design ◽  
Single Error ◽  
Half Duplex ◽  
Communication Module ◽  
Forward Error

The Universal Asynchronous Receiver Transmitter (UART) is the very simple and significant sequential communication protocol which is basically utilized for microprocessors & microcontroller systems. It is a shorter range communication protocol, which able to perform half-duplex and full-duplex type of communication at baud rates. Though, UART is a type of shorter range communication still they are not resistant to noisy channel which leads to communication errors by flipping or loosing of bits. These kinds of signal errors are named as forward-errors. The correction of forward errors is a mechanism to handle and rectify those errors (i.e. Burst errors and Random bits error). Thus in this methodology, have introduced a UART-SEC-DED communication module design which utilizes the Hamming encoder and decoders to achieve the forward error correction. Finally, the proposed system will simulated and implemented on FPGA board and experimental outcomes shows the better efficiency in single error correction and detection of double errors.  

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