scholarly journals A High-Reliability Redundancy Scheme for Design of Radiation-Tolerant Half-Duty Limited DC-DC Converters

Electronics ◽  
2021 ◽  
Vol 10 (10) ◽  
pp. 1146
Author(s):  
Solomon Mamo Banteywalu ◽  
Getachew Bekele ◽  
Baseem Khan ◽  
Valentijn De Smedt ◽  
Paul Leroux
Keyword(s):  
Fault Tolerant ◽  
High Reliability ◽  
Hybrid Technique ◽  
Space Applications ◽  
Forward Converter ◽  
Overhead Cost ◽  
Single Fault ◽  
Area Overhead ◽  
Fault Masking ◽  
Radiation Tolerant

Redundancy techniques are commonly used to design radiation- and fault-tolerant circuits for space applications, to ensure high reliability. However, higher reliability often comes at a cost of increased usage of hardware resources. Triple Modular Redundancy (TMR) ensures full single fault masking, with a >200% power and area overhead cost. TMR/Simplex ensures full single fault masking with a slightly more complicated circuitry, inefficient use of resource and a >200% power and area overhead cost, but with higher reliability than that of TMR. In this work, a high-reliability Spatial and Time Redundancy (TR) hybrid technique, which does not abandon a working module and is applicable for radiation hardening of half-duty limited DC-DC converters, is proposed and applied to the design of a radiation-tolerant digital controller for a Dual-Switch Forward Converter. The technique has the potential of double fault masking with a <2% increase in resource overhead cost compared to TMR. Moreover, for a Simplex module failure rate, λ, of 5%, the Reliability Improvement Factor (RIF) over the Simplex system is 20.8 and 500 for the proposed technique’s two- and three-module implementations, respectively, compared to a RIF over the Simplex system of only 7.25 for TMR and 14.3 for the regular TMR/Simplex scheme.

scholarly journals A Fault Tolerant Voter for Approximate Triple Modular Redundancy

Electronics ◽  
2019 ◽  
Vol 8 (3) ◽  
pp. 332 ◽  
Author(s):  
Tooba Arifeen ◽  
Abdus Hassan ◽  
Jeong-A Lee
Keyword(s):  
Fault Tolerant ◽  
Triple Modular Redundancy ◽  
Area Overhead ◽  
Final Output ◽  
Working Principle ◽  
Fault Masking ◽  
Internal Faults ◽  
Modular Redundancy ◽  
Power Delay Product

Approximate Triple Modular Redundancy has been proposed in the literature to overcome the area overhead issue of Triple Modular Redundancy (TMR). The outcome of TMR/Approximate TMR modules serves as the voter input to produce the final output of a system. Because the working principle of Approximate TMR conditionally allows one of the approximate modules to differ from the original circuit, it is critical for Approximate TMR that a voter not only be tolerant toward its internal faults but also toward faults that occur at the voter inputs. Herein, we present a novel compact voter for Approximate TMR using pass transistors and quadded transistor level redundancy to achieve a higher fault masking. The design also targets a better Quality of Circuit (QoC), a new metric which we have proposed for highlighting the ability of a circuit to fully mask all possible internal faults for an input vector. Comparing the fault masking features with those of existing works, the proposed voter delivered upto 45.1%, 62.5%, 26.6% improvement in Fault Masking Ratio (FMR), QoC, and reliability, respectively. With respect to the electrical characteristics, our proposed voter can achieve an improvement of up to 50% and 56% in terms of the transistor count and power delay product, respectively.

SpaceWire Inspired Network-on-Chip Approach for Fault Tolerant System-on-Chip Designs

2010 ◽  
pp. 293-308
Author(s):  
Björn Osterloh ◽  
Harald Michalik ◽  
Björn Fiethe
Keyword(s):  
Fault Tolerant ◽  
High Reliability ◽  
Dynamic Reconfiguration ◽  
Network On Chip ◽  
System On Chip ◽  
Space Applications ◽  
Communication Architecture ◽  
Radiation Induced ◽  
And Performance ◽  
On Chip

Today FPGAs with large gate counts provide a highly flexible platform to implement a complete System-on-Chip (SoC) in a single device. Specifically radiation tolerant space suitable SRAM-based FPGAs have significantly improved the flexibility of high reliable systems for space applications. Currently the reconfigurability of these devices is only used during development phase. A further enhancement would be using the reconfigurability of SRAM-FPGAs in space, either to statically update or dynamically reconfigure processing modules. This is a major improvement in terms of maintenance and performance, which is essential for scientific instruments in space. The requirement for this enhanced system is to guarantee the system qualification and retain the achieved high reliability. Therefore effects during the reconfiguration process and interference of updated modules on the system have to be prevented. Updated modules need to be isolated physically and logically by qualified communication architecture. In this chapter the advantage of a specialized Network-on-Chip architecture to achieve a high reliable SoC with dynamic reconfiguration capability is presented. The requirements for SoC based on SRAM-FPGA in high reliable applications are outlined. Additionally the influences of radiation induced particles are described and effects during the dynamic reconfiguration are discussed. A specialized Network-on-Chip architecture is then proposed and its advantages are presented.

scholarly journals Issues in Design and Development of Reliable Configurable Distributed Checkout and Launch System for Mission Critical Aero-Space Flight Vehicles

2020 ◽  
Vol 9 (4S2) ◽  
pp. 77-81
Keyword(s):  
System Reliability ◽  
Fault Tolerant ◽  
High Reliability ◽  
Critical Parameters ◽  
Health Checks ◽  
Flight Vehicles ◽  
Mission Critical ◽  
Criticality Analysis

Role of Configurable Distributed Checkout and Launch System (CDCLS) is pivotal in carrying out quick health checks and launching of Aerospace Flight Vehicles. Configurable Distributed Architecture provides flexibility for connecting nodes and scaling Distributed System. Different configurations can be derived from the Master Configuration. Since, Ultra high reliability and infallible performance of the CDCLS is of paramount importance, Safety criticality and Mission criticality analysis needs to be carried out for determination of mission critical parameters. These critical parameters need to be addressed by required fault tolerant architecture, which can be implemented in Hardware and Software for achieving system reliability objective (Say, 0.99).

scholarly journals Planning Fail-Safe Trajectories for Space Robotic Arms

2021 ◽  
Vol 8 ◽  
Author(s):  
Oliver Porges ◽  
Daniel Leidner ◽  
Máximo A. Roa
Keyword(s):  
Degrees Of Freedom ◽  
Fault Tolerant ◽  
Robotic Manipulators ◽  
Task Completion ◽  
Joint Failure ◽  
Space Applications ◽  
Robotic Arms ◽  
Hazardous Environments ◽  
Potential Risks ◽  
Fail Safe

A frequent concern for robot manipulators deployed in dangerous and hazardous environments for humans is the reliability of task executions in the event of a joint failure. A redundant robotic manipulator can be used to mitigate the risk and guarantee a post-failure task completion, which is critical for instance for space applications. This paper describes methods to analyze potential risks due to a joint failure, and introduces tools for fault-tolerant task design and path planning for robotic manipulators. The presented methods are based on off-line precomputed workspace models. The methods are general enough to cope with robots with any type of joint (revolute or prismatic) and any number of degrees of freedom, and might include arbitrarily shaped obstacles in the process, without resorting to simplified models. Application examples illustrate the potential of the approach.

DESIGN OF A MULTI-LEVEL FAULT-TOLERANT MESH (MFTM) FOR HIGH RELIABILITY APPLICATIONS

1995 ◽  
Vol 02 (04) ◽  
pp. 419-429
Author(s):  
SHAMBHU J. UPADHYAYA ◽  
I-SHYAN HWANG
Keyword(s):  
System Reliability ◽  
Fault Tolerant ◽  
High Reliability ◽  
Operational Reliability ◽  
Variable Number ◽  
Hierarchical Design ◽  
Processor Arrays ◽  
Design Paradigm ◽  
Multi Level ◽  
Overall Reliability

This paper presents a novel technique for the enhancement of operational reliability of processor arrays by a multi-level fault-tolerant design approach. The key idea of the design is based on the well known hierarchical design paradigm. The proposed fault-tolerant architecture uses a flexible reconfiguration of redundant nodes, thereby offering a better spare utilization than existing two-level redundancy schemes. A variable number of spares is provided at each level of redundancy which enables a flexible reconfiguration as well as area efficient layouts and better spare utilization. The spare nodes at each level can replace any of the failed primary nodes, not only at the same level but also those at the lower levels. The architecture can be adopted to increase the system reliability in Multi Chip Modules (MCMs). The main contributions of our work are the higher degree of fault tolerance, higher overall reliability, flexibility, and a better spare utilization.

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