scholarly journals Design and Analysis of Fault-Tolerant 1:2 Demultiplexer Using Quantum-Dot Cellular Automata Nano-Technology

Electronics ◽  
2021 ◽  
Vol 10 (21) ◽  
pp. 2565
Author(s):  
Saeid Seyedi ◽  
Nima Jafari Navimipour ◽  
Akira Otsuki

Quantum-dot Cellular Automata (QCA) is an innovative paradigm bringing hopeful applications in the perceptually novel computing layout in quantum electronics. The circuits manufactured by QCA technology can provide a notable decrease in size, rapid-switching velocity, and ultra-low power utilization. The demultiplexer is a beneficial component to optimize the whole process in any logical design, and therefore is very important in QCA. Moreover, fault-tolerant circuits can improve the reliability of digital circuits by redundancy. Hence, the present investigation illustrates a novel QCA-based fault-tolerant 1:2 demultiplexer construct that employs a two-input AND gate and inverter. The functionality of the suggested layout was executed and evaluated with the utilization of the QCADesigner 2.0.3 simulator. This paper utilizes cell redundancy on the wire, inverter, and AND gates for designing a fault-tolerant demultiplexer. Four components (i.e., missing cells, dislocation cells, extra cells, and misalignment) were analyzed by the QCADesigner simulator. The simulation results demonstrated that our proposed QCA-based fault-tolerant 1:2 demultiplexer acted more efficiently than prior constructs regarding delay and fault tolerance. The proposed fault-tolerant 1:2 demultiplexer could attain high fault-tolerance when single missing cell or extra cell faults exist in the QCA layout.

2012 ◽  
Vol 2012 ◽  
pp. 1-7 ◽  
Author(s):  
Razieh Farazkish ◽  
Samira Sayedsalehi ◽  
Keivan Navi

Quantum-dot Cellular Automata (QCA) is one of the most attractive technologies for computing at nanoscale. The principle element in QCA is majority gate. In this paper, fault-tolerance properties of the majority gate is analyzed. This component is suitable for designing fault-tolerant QCA circuits. We analyze fault-tolerance properties of three-input majority gate in terms of misalignment, missing, and dislocation cells. In order to verify the functionality of the proposed component some physical proofs using kink energy (the difference in electrostatic energy between the two polarization states) and computer simulations using QCA Designer tool are provided. Our results clearly demonstrate that the redundant version of the majority gate is more robust than the standard style for this gate.


2018 ◽  
Vol 16 (01) ◽  
pp. 1850010 ◽  
Author(s):  
Golnaz Bahadori ◽  
Monireh Houshmand ◽  
Mariam Zomorodi-Moghadam

Quantum-dot cellular automata (QCA) is a promising emerging nanotechnology that has been attracting considerable attention due to its small feature size, ultra-low power consuming, and high clock frequency. Therefore, there have been many efforts to design computational units based on this technology. Despite these advantages of the QCA-based nanotechnologies, their implementation is susceptible to a high error rate. On the other hand, using the reversible computing leads to zero bit erasures and no energy dissipation. As the reversible computation does not lose information, the fault detection happens with a high probability. In this paper, first we propose a fault-tolerant control unit using reversible gates which improves on the previous design. The proposed design is then synthesized to the QCA technology and is simulated by the QCADesigner tool. Evaluation results indicate the performance of the proposed approach.


2020 ◽  
Vol 18 (06) ◽  
pp. 2050032
Author(s):  
Suhaib Ahmed ◽  
Syed Farah Naz

The issues faced by Complementary metal oxide semi-conductor (CMOS) technology in the nanoregime have led to the research of other possible technologies which can operate with same functionalities however, with higher speed and lower power dissipation. One such technology is Quantum-dot Cellular Automata (QCA). At present, logic circuit designs using QCA have been comprehensively researched and one such application area being investigated is data transmission. Various data transfer techniques for reliable data transfer are available and among them convolution coding is being widely used in mobile, radio and satellite communications. Considering the evolution towards nano communication networks, in this paper an ultra-proficient designs of 1/2 rate and 1/3 rate convolution encoders based on a cost-efficient and fault tolerant XOR gate design have been proposed for application in nano communication networks. Based on the performance analysis, it is observed that the proposed designs are efficient in respect to cell count, area, delay and circuit cost and achieves performance improvement up to 40.21% for 1/2 encoder and 31.81% for 1/3 encoder compared to the best design in the literature. In addition to this, the energy dissipation analysis of the proposed designs is also presented. The proposed designs can thus be efficiently utilized in various nanocommunication applications requiring minimal area and ultra-low power consumption.


2021 ◽  
Vol 13 ◽  
Author(s):  
Neeraj Tripathi ◽  
Mohammad Mudakir Fazili ◽  
Rahil Jahangir

Aim: A novel design for non-reversible as well as reversible parity generator and detector in Quantum-dot Cellular Automata (QCA) technology is presented in this research article. Parity generator and detector circuits are reliable error-checking components of a nano-communication system. Objective: The main focus of this research is to design an ultra-low-power fault-tolerant reversible gate implementation of the parity logic function in QCA. An efficient QCA design layout with minimal area, less latency and the least energy dissipation is desired. Methods: The proposed designs are developed using Quantum-dot Cellular Automata (QCA) technology. The circuits are optimized using majority gate reduction and clock zone reduction techniques. Also, the cell-cell interaction technique is employed to further optimize the QCA circuit. To increase the fault tolerance and for ultra-low power operation, reversible QCA circuits are designed using cascaded Feynman gates. Results and Conclusion: The efficiency of the parity generator and detector is calculated to be more than 25% compared to existing QCA layouts. It is demonstrated in this paper that the proposed circuits perform exceptionally well on every design parameter. The design parameters under consideration are cell count, cell area, complexity, crossover count, latency and energy dissipation. Using reversible logic, a fault-tolerant and defect-sensitive circuit is developed for parity generation and detection.


2021 ◽  
Author(s):  
Yaser Rahmani ◽  
Saeed Rasouli Heikalabad ◽  
Mohammad Mosleh

Abstract Quantum-dot Cellular Automata (QCA) technology is believed to be a good alternative to CMOS technology. This nanoscale technology can provide a platform for design and implementation of high performance and power efficient logic circuits. However, the fabrication of QCA circuits is susceptible to faults appearing in this form of missing cells, additional cells, rotated cells, and displaced cells. Over the years, several solutions have been proposed to address these problems. This paper presents a new solution for improving the fault tolerance of three input majority gate. The proposed majority gate is then used to design 2-1 multiplexer and 4-1 multiplexer. The proposed designs are implemented in QCA Designer. Simulation results demonstrate significant improvements in terms of fault tolerance and area requirement.


2005 ◽  
Vol 98 (9) ◽  
pp. 094904 ◽  
Author(s):  
M. Khatun ◽  
T. Barclay ◽  
I. Sturzu ◽  
P. D. Tougaw

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