scholarly journals Unbalanced-Tests to the Improvement of Yield and Quality

Electronics ◽  
2021 ◽  
Vol 10 (23) ◽  
pp. 3032
Author(s):  
Chung-Huang Yeh ◽  
Jwu-E Chen
Keyword(s):  
Integrated Circuit ◽  
Large Scale ◽  
Manufacturing Industry ◽  
Product Distribution ◽  
Test Method ◽  
Distribution Model ◽  
Threshold Test ◽  
Yield And Quality ◽  
Large Scale Integration ◽  
Scale Integration

An integrated-circuit testing model (DITM) is used to describe various factors that affect test yield during a test process. We used a probability distribution model to evaluate test yield and quality and introduced a threshold test and a guardband test. As a result of the development speed of the semiconductor manufacturing industry in the future being unpredictable, we use electrical properties of existing products and the current manufacturing technology to estimate future product-distribution trends. In the development of very-large-scale integration (VLSI) testing, the progress of testing technology is very slow. To improve product testing yield and quality, we change the test method and propose an unbalanced-test method, leading to improvements in test results. The calculation using our proposed model and data estimated by the product published by the IEEE International Roadmap for Devices and Systems (IRDS, 2017) proves that the proposed unbalanced-test method can greatly improve test yield and quality and achieve the goal of high-quality, near-zero-defect products.

scholarly journals Vlsi Interconnection Modelling Using a Finite Element Approach

1995 ◽  
Vol 18 (3) ◽  
pp. 179-202
Author(s):  
Umesh Kumar
Keyword(s):  
Integrated Circuit ◽  
Large Scale ◽  
Low Complexity ◽  
Stratified Medium ◽  
Base Function ◽  
Large Scale Integration ◽  
Element Approach ◽  
Scale Integration ◽  
High Degree ◽  
Important Shift

In the last decade, an important shift has taken place in the design of hardware with the advent of smaller and denser integrated circuit packages. Analysis techniques are required to ensure the proper electrical functioning of this hardware. An efficient method is presented to model the parasitic capacitance of VLSI (very large scale integration) interconnections. It is valid for conductors in a stratified medium, which is considered to be a good approximation for theSi−SiO2system of which present day ICs are made. The model approximates the charge density on the conductors as a continuous function on a web of edges. Each base function in the approximation has the form of a “spider” of edges. Here the method used [1] has very low complexity, as compared to other models used previously [2], and achieves a high degree of precision within the range of validity of the stratified medium.

scholarly journals PERANCANGAN MULTIPLIER SEKUENSIAL 8-BIT DENGAN TEKNOLOGI 180NM MENGGUNAKAN PERANGKAT LUNAK ELECTRIC

TRANSIENT ◽  
2017 ◽  
Vol 6 (3) ◽  
pp. 476
Author(s):  
Brama Yoga Satria ◽  
Munawar Agus Riyadi ◽  
Muhammad Arfan
Keyword(s):  
Integrated Circuit ◽  
Large Scale ◽  
Very Large Scale Integration ◽  
Shift Register ◽  
Large Scale Integration ◽  
Scale Integration ◽  
Logic Unit

Very Large Scale Integration (VLSI) merupakan proses dari pembuatan sirkuit terpadu atau Integrated Circuit (IC) dengan cara menggabungkan ribuan rangkaian berbasis transistor ke dalam sebuah chip atau prosesor. Dengan adanya VLSI, ukuran dari devais elektronik berbasis transistor dapat dimampatkan agar menghemat area, biaya produksi, dan efek parasitik. Prosesor terdiri dari beberapa blok utama sebagai penunjang kerjanya, salah satu blok yang paling penting yaitu Arithmatic  Logic Unit (ALU). Salah satu contoh dari ALU sendiri yaitu adalah multiplier. Multiplier sangat penting untuk banyak dasar proses dari sebuah prosesor. Tujuan dari penelitian ini adalah merancang sebuah multiplier sekuensial 8-bit dengan teknologi 180nm. Multiplier dirancang dengan menggabungkan blok-blok pembangun seperti blok counter, adder, shift register, dan lain-lainnya. Penelitian ini menggunakan perangkat lunak electric untuk mendesain layout dan perangkat lunak LT-Spice untuk menguji fungsional, delay, dan kinerja dari hasil ekstraksi layout. Hasil perancangan ini secara fungsional telah berjalan dengan baik. Multiplier yang dirancang memiliki layout sebesar 3.725.150 lambda2 dengan nilai delay sebesar 4,428ns. Selain itu, frekuensi maksimum yang digunakan untuk mendapatkan hasil yang benar dari multiplier sekuensial 8-bit yaitu 50MHz.

An Approach to Reading Machine Design

1978 ◽  
Vol 20 (3) ◽  
pp. 287-293 ◽  
Author(s):  
Jonathan Allen
Keyword(s):  
Integrated Circuit ◽  
Large Scale ◽  
Read Aloud ◽  
Machine Design ◽  
Current Status ◽  
Text To Speech ◽  
Short Term ◽  
Large Scale Integration ◽  
Scale Integration ◽  
Circuit Technology

Within two years, both the required algorithmic competence and the necessary integrated circuit technology will have been developed to a point where practical personal reading machines for the blind will be possible. In this paper, the linguistic and phonetic principles needed to convert optically recognized text to speech are discussed, and it is shown how they mirror the human cognitive ability to read aloud. A perspective on the current status and rate of progress of large scale integration technology is then used to show that economical implementations of even complex text-to-speech algorithms can be realized in the short-term future. Finally, a view of important human factors problems requiring attention is given.

Silicide Applications In Microelectronics

1981 ◽  
Vol 10 ◽  
Author(s):  
Billy L. Crowder
Keyword(s):  
Integrated Circuit ◽  
Polycrystalline Silicon ◽  
Large Scale ◽  
Field Effect Transistor ◽  
Oxide Semiconductor ◽  
Device Structures ◽  
Direct Replacement ◽  
Large Scale Integration ◽  
Effect Transistor ◽  
Scale Integration

ABSTRACTThe advent of very-large-scale integration in microelectronics has been achieved by reduction in lithographic dimensions coupled with a corresponding decrease in vertical dimensions in properly scaled device structures. This development has placed severe demands upon interconnection technology. The practice of using semiconducting regions (diffusions or polycrystalline silicon) for interconnecting devices is no longer viable because of the high resistance associated with such regions (i.e. interconnections do not “scale” properly). One solution to this problem is the use of multilevel metallization, but this requires tens of thousands of small contacts to shallow diffusions. Refractory metals such as titanium are being explored as materials which provide the necessary stable low resistance contacts suitable for integrated circuit applications. Another solution to the problem is to develop a higher conductivity material to replace or supplement polycrystalline silicon. Refractory metal disilicides have been extensively investigated for this application -both as a direct replacement for polycrystalline silicon or in a silicide/polycrystalline silicon composite (polycide). A critical review of the present status in both these areas will be presented. Emphasis will be upon our experience gained in conjunction with the development of a 1 μm silicon gate metal/oxide/ semiconductor field effect transistor technology.

The Integration on Electrical Control Systems Based on Optimized Method

2012 ◽  
Vol 490-495 ◽  
pp. 2604-2608
Author(s):  
Ai Rong Zhang
Keyword(s):  
Integrated Circuit ◽  
Large Scale ◽  
Vlsi Design ◽  
Hardware Architecture ◽  
Logic Device ◽  
Integrated Circuit Design ◽  
Large Scale Integration ◽  
Hardware Description ◽  
Description Languages ◽  
Scale Integration

Very large scale integration (VLSI) applications have improved control implementation performance. Indeed, an application specific integrated circuit (ASIC) solution can exploit efficiently specificities of the control algorithms that fixed hardware architecture cannot do. For example, parallel calculation cannot be included in a software solution based on sequential processing. In addition, ASIC can reduce wire and electromagnetic field interference by a fully system on a chip (SoC) integration. However, there are still two main drawbacks to an integrated circuit solution: design complexity and reuse difficulty. This is true even with programmable logic device (PLD) solutions. Conception aid developer (CAD) combined with hardware description languages (HDL) and VLSI design methodology have accelerated conception and reuse. Nevertheless, the main problem of integrated circuit design is to define the hardware architecture; this is particularly true for heterogeneous algorithm structures such as electrical controls.

Impact of driver size and interwire parasitics on crosstalk noise and delay

2014 ◽  
Vol 12 (4) ◽  
pp. 475-490
Author(s):  
Devendra Kumar Sharma ◽  
Brajesh Kumar Kaushik ◽  
R.K. Sharma
Keyword(s):  
Integrated Circuit ◽  
Large Scale ◽  
Propagation Delay ◽  
Combined Effects ◽  
Crosstalk Noise ◽  
Content Type ◽  
Coupling Capacitance ◽  
Large Scale Integration ◽  
Scale Integration ◽  
Coupling Parasitics

Purpose – The purpose of this research paper is to analyze the combined effects of driver size and coupling parasitics on crosstalk noise and delay for static and dynamically switching victim line. Furthermore, this paper shows the effect of inductance on delay and qualitatively optimizes its value to obtain minimum delay. Design/methodology/approach – The interwire parasitics are the primary sources of crosstalk or coupled noise that may lead to critical delays/logic malfunctions. This paper is based on simulating a pair of distributed resistance inductance capacitance (RLC) interconnects coupled capacitively and inductively for measurements of crosstalk noise/delay. The combined effects of driver sizing and interwire parasitics on peak overshoot noise/delay are observed through simulation program with integrated circuit emphasis (SPICE) simulations for different switching patterns. Furthermore, the analysis of inductive effect on propagation delay as a function of coupling capacitance is carried out and the optimization of delay is worked out qualitatively. The simulations are carried out at 0.13 μm, 1.5 V technology node. Findings – This paper observes the contradictory effects of coupling parasitics on wire propagation delay; however, the effect on peak noise is of a different kind. Further, this paper shows that the driver size exhibits opposite kind of behavior on propagation delay than peak over shoot noise. It is observed that the delay is affected in presence of inductance; thus, the optimization of delay is carried out. Originality/value – The effects of driver sizing and interwire parasitics are analyzed through simulations. The optimum value of coupling capacitance for delay is found qualitatively. These findings are important for designing very large scale integration (VLSI) interconnects.

Voltage contrast: A powerful tool for VLSI circuit diagnosis

1983 ◽  
Vol 41 ◽  
pp. 164-167
Author(s):  
A. R. Stivers
Keyword(s):  
Integrated Circuit ◽  
Large Scale ◽  
Vlsi Circuits ◽  
Current Drive ◽  
Beam Voltage ◽  
Capacitive Load ◽  
Large Scale Integration ◽  
High Resolution Images ◽  
Voltage Contrast ◽  
Scale Integration

The advent of very large scale integration (VLSI) presents many new problems for integrated circuit (I.C.) diagnosis. Some I.C.s have over 100,000 transistors with less than 100 external leads with which the transistors can be tested. The geometries are now as small as 3 μm, smaller than can be probed mechanically. Along with the size, node capacitance and current drive are also reduced making a probe's capacitive load very detrimental to rise-time measurements. New processes have many layers of interconnect, leaving more and more of the circuit below passivation and therefore inaccessible to a mechanical probe, even after the removal of scratch protection. VLSI challenges I.C. diagnosis with more internal circuitry that becomes smaller and less accessible to conventional probes.Voltage contrast is an electron beam voltage probing technique especially suited to VLSI circuits. A properly modified SEM, used in the voltage contrast mode, provides both high resolution images of circuit voltages and also voltage waveforms of particular nodes.

Plant hormones, plant growth regulators

2014 ◽  
Vol 155 (26) ◽  
pp. 1011-1018 ◽  
Author(s):  
György Végvári ◽  
Edina Vidéki
Keyword(s):  
Nervous System ◽  
Growth And Development ◽  
Large Scale ◽  
Essential Role ◽  
Higher Plants ◽  
Structure And Function ◽  
Wide Sense ◽  
Large Scale Integration ◽  
Scale Integration ◽  
And Function

Plants seem to be rather defenceless, they are unable to do motion, have no nervous system or immune system unlike animals. Besides this, plants do have hormones, though these substances are produced not in glands. In view of their complexity they lagged behind animals, however, plant organisms show large scale integration in their structure and function. In higher plants, such as in animals, the intercellular communication is fulfilled through chemical messengers. These specific compounds in plants are called phytohormones, or in a wide sense, bioregulators. Even a small quantity of these endogenous organic compounds are able to regulate the operation, growth and development of higher plants, and keep the connection between cells, tissues and synergy beween organs. Since they do not have nervous and immume systems, phytohormones play essential role in plants’ life. Orv. Hetil., 2014, 155(26), 1011–1018.

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