scholarly journals Mapping Arbitrary Logic Functions onto Carry Chains in FPGAs

Electronics ◽  
2021 ◽  
Vol 11 (1) ◽  
pp. 27
Author(s):  
Raouf Senhadji-Navarro ◽  
Ignacio Garcia-Vargas
Keyword(s):  
Bin Packing ◽  
Critical Path ◽  
Conventional Technique ◽  
Test Cases ◽  
Logic Function ◽  
Mapping Algorithm ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Logic Functions

Current Field Programmable Gate Arrays (FPGAs) provide fast routing links and special logic to perform carry operations; however, these resources can also be used to implement non-arithmetic circuits. In this paper, a new approach for mapping logic functions onto carry chains is presented. Unlike other approaches, the proposed technique can be applied to any logic function. The presented technique includes: (1) an architecture that is composed of blocks that implement AND and OR functions (called CANDs and CORs, respectively) by means of Look-Up-Tables (LUTs) and carry-chain resources; and (2) a mapping algorithm to reduce both the delay of the critical path and the number of used FPGA resources. The algorithm uses a heuristic to interconnect CORs and CANDs in order to reduce the delay. The problem of mapping the maxterms (or minterms) of a function to LUTs has been modelled as a Set Bin Packing (SBP) problem. Since SBP is NP-Hard, a greedy algorithm has been proposed, which is based on the First Fit Decreasing (FFD) heuristic. The results obtained have been compared with the conventional technique using both speed and area optimization. For this purpose, a large synthetic set of test cases has been generated. The proposed technique improves both the speed and area results for the vast majority of functions whose conventional implementation requires more than four logic levels. It is important to highlight that the improvement of one parameter (speed or area) is not achieved at the expense of the other.

scholarly journals Exploring Shared SRAM Tables in FPGAs for Larger LUTs and Higher Degree of Sharing

2017 ◽  
Vol 2017 ◽  
pp. 1-9 ◽  
Author(s):  
Ali Asghar ◽  
Muhammad Mazher Iqbal ◽  
Waqar Ahmed ◽  
Mujahid Ali ◽  
Husain Parvez ◽  
...  
Keyword(s):  
High Performance ◽  
Critical Path ◽  
Path Delay ◽  
Gate Arrays ◽  
Area Reduction ◽  
Area Overhead ◽  
Logic Block ◽  
Field Programmable ◽  
Boolean Matching ◽  
Programmable Gate Arrays

In modern SRAM based Field Programmable Gate Arrays, a Look-Up Table (LUT) is the principal constituent logic element which can realize every possible Boolean function. However, this flexibility of LUTs comes with a heavy area penalty. A part of this area overhead comes from the increased amount of configuration memory which rises exponentially as the LUT size increases. In this paper, we first present a detailed analysis of a previously proposed FPGA architecture which allows sharing of LUTs memory (SRAM) tables among NPN-equivalent functions, to reduce the area as well as the number of configuration bits. We then propose several methods to improve the existing architecture. A new clustering technique has been proposed which packs NPN-equivalent functions together inside a Configurable Logic Block (CLB). We also make use of a recently proposed high performance Boolean matching algorithm to perform NPN classification. To enhance area savings further, we evaluate the feasibility of more than two LUTs sharing the same SRAM table. Consequently, this work explores the SRAM table sharing approach for a range of LUT sizes (4–7), while varying the cluster sizes (4–16). Experimental results on MCNC benchmark circuits set show an overall area reduction of ~7% while maintaining the same critical path delay.

Enhanced Technology Mapping for FPGAs with Exploration of Cell Configurations

2015 ◽  
Vol 24 (03) ◽  
pp. 1550039 ◽  
Author(s):  
Grace Zgheib ◽  
Iyad Ouaiss
Keyword(s):  
State Of The Art ◽  
Variable Structure ◽  
Logic Circuits ◽  
Technology Mapping ◽  
Decomposition Techniques ◽  
Gate Arrays ◽  
Field Programmable ◽  
Boolean Matching ◽  
Programmable Gate Arrays ◽  
Logic Functions

In the state-of-the-art field-programmable gate arrays (FPGAs), logic circuits are synthesized and mapped on clusters of look-up tables. However, arithmetic operations benefit from an existing dedicated adder along with a carry chain used to ensure a fast carry propagation. This carry chain is a dedicated wire available in the architecture of the FPGA and is as such independent of the external programmable routing resources. In this paper, we propose a variable-structure Boolean matching technology mapper with embedded decomposition techniques to map nonarithmetic logic functions on carry chains. Previously synthesized and mapped logic functions are adapted so that their outputs are routed using the dedicated carry chains instead of the external programmable interconnects. The experimental results show a reduction in the used routing resources as well as the circuit area when using this Boolean matching-based mapper on the Altera Stratix-III FPGA.

scholarly journals FPGA-Based Controller for a Hybrid Grid-Connected PV/Wind/Battery Power System with AC Load

Energies ◽  
2021 ◽  
Vol 14 (8) ◽  
pp. 2108
Author(s):  
Mohamed Yassine Allani ◽  
Jamel Riahi ◽  
Silvano Vergura ◽  
Abdelkader Mami
Keyword(s):  
Fuzzy Logic ◽  
Hybrid System ◽  
High Voltage ◽  
Field Programmable Gate Arrays ◽  
Energy System ◽  
Maximum Power ◽  
Hybrid Energy ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays

The development and optimization of a hybrid system composed of photovoltaic panels, wind turbines, converters, and batteries connected to the grid, is first presented. To generate the maximum power, two maximum power point tracker controllers based on fuzzy logic are required and a battery controller is used for the regulation of the DC voltage. When the power source varies, a high-voltage supply is incorporated (high gain DC-DC converter controlled by fuzzy logic) to boost the 24 V provided by the DC bus to the inverter voltage of about 400 V and to reduce energy losses to maximize the system performance. The inverter and the LCL filter allow for the integration of this hybrid system with AC loads and the grid. Moreover, a hardware solution for the field programmable gate arrays-based implementation of the controllers is proposed. The combination of these controllers was synthesized using the Integrated Synthesis Environment Design Suite software (Version: 14.7, City: Tunis, Country: Tunisia) and was successfully implemented on Field Programmable Gate Arrays Spartan 3E. The innovative design provides a suitable architecture based on power converters and control strategies that are dedicated to the proposed hybrid system to ensure system reliability. This implementation can provide a high level of flexibility that can facilitate the upgrade of a control system by simply updating or modifying the proposed algorithm running on the field programmable gate arrays board. The simulation results, using Matlab/Simulink (Version: 2016b, City: Tunis, Country: Tunisia, verify the efficiency of the proposed solution when the environmental conditions change. This study focused on the development and optimization of an electrical system control strategy to manage the produced energy and to coordinate the performance of the hybrid energy system. The paper proposes a combined photovoltaic and wind energy system, supported by a battery acting as an energy storage system. In addition, a bi-directional converter charges/discharges the battery, while a high-voltage gain converter connects them to the DC bus. The use of a battery is useful to compensate for the mismatch between the power demanded by the load and the power generated by the hybrid energy systems. The proposed field programmable gate arrays (FPGA)-based controllers ensure a fast time response by making control executable in real time.

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