scholarly journals An N/M-Ratio All-Digital Clock Generator with a Pseudo-NMOS Comparator-Based Programmable Divider

Electronics ◽  
2022 ◽  
Vol 11 (2) ◽  
pp. 261
Author(s):  
Jongsun Kim
Keyword(s):  
Power Consumption ◽  
Small Area ◽  
High Speed ◽  
Propagation Delay ◽  
Low Power Consumption ◽  
Cmos Process ◽  
Clock Generator ◽  
Frequency Multiplication ◽  
Digital Clock ◽  
Delay Locked Loop

A multiplying delay-locked loop (MDLL)-based all-digital clock generator with a programmable N/M-ratio frequency multiplication capability for digital SoC is presented. The proposed digital MDLL provides programmable N/M-ratio frequency multiplication using a new high-speed Pseudo-NMOS comparator-based programmable divider with small area and low power consumption. The proposed MDLL clock generator can also provide a de-skew function by eliminating the phase offset problem caused by the propagation delay of the front divider in conventional N/M MDLL architectures. Fabricated in a 0.13-µm 1.2-V CMOS process, the proposed digital MDLL clock generates fully de-skewed output clock frequencies from 0.3 to 1.137 GHz with programmable N/M ratios of N = 1~32 and M = 1~16. It achieves a measured effective peak-to-peak jitter of 12 ps at 1.0 GHz when N/M = 8/1. It occupies an active area of only 0.034 mm2 and consumes a power of 10.3 mW at 1.0 GHz.

A NOVEL SWITCHED-CURRENT SUCCESSIVE APPROXIMATION ADC

2011 ◽  
Vol 20 (01) ◽  
pp. 15-27 ◽  
Author(s):  
XIAN TANG ◽  
KONG PANG PUN
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Successive Approximation ◽  
High Speed ◽  
High Accuracy ◽  
Low Power Consumption ◽  
Cmos Process ◽  
Power Efficient ◽  
Successive Approximation Adc ◽  
Switched Current

A novel switched-current successive approximation ADC is presented in this paper with high speed and low power consumption. The proposed ADC contains a new high-accuracy and power-efficient switched-current S/H circuit and a speed-improved current comparator. Designed and simulated in a 0.18-μm CMOS process, this 8-bit ADC achieves 46.23 dB SNDR at 1.23 MS/s consuming 73.19 μW under 1.2 V voltage supply, resulting in an ENOB of 7.38-bit and an FOM of 0.357 pJ/Conv.-step.

scholarly journals The Cascade Carry Array Multiplier – A Novel Structure of Digital Unsigned Multipliers for Low-Power Consumption and Ultra-Fast Applications

2019 ◽  
Vol 3 (3) ◽  
pp. 19-27
Author(s):  
Mohsen Sadeghi ◽  
Mahya Zahedi ◽  
Maaruf Ali
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Supply Voltage ◽  
Circuit Simulation ◽  
Propagation Delay ◽  
Simulation Software ◽  
Low Power Consumption ◽  
Ultra Low Power ◽  
Novel Structure

This article presents a low power consumption, high speed multiplier, based on a lowest transistor count novel structure when compared with other traditional multipliers. The proposed structure utilizes 4×4-bit adder units, since it is the base structure of digital multipliers. The main merits of this multiplier design are that: it has the least adder unit count; ultra-low power consumption and the fastest propagation delay in comparison with other gate implementations. The figures demonstrate that the proposed structure consumes 32% less power than using the bypassing Ripple Carry Array (RCA) implementation. Moreover, its propagation delay and adder units count are respectively about 31% and 8.5% lower than the implementation using the bypassing RCA multiplier. All of these simulations were carried out using the HSPICE circuit simulation software in 0.18 μm technology at 1.8 V supply voltage. The proposed design is thus highly suitable in low power drain and high-speed arithmetic electronic circuit applications.

scholarly journals High Speed and Low Power Consumption by Exploitation using Novel XOR and XNOR Gates

2019 ◽  
Vol 8 (12S) ◽  
pp. 1182-1186
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Short Circuit ◽  
Full Adder ◽  
Low Power Consumption ◽  
Cmos Process ◽  
Input Noise ◽  
Threshold Voltages ◽  
Output Capacitance

The present paper proposes a high speed and low power consumption by travelling novel XOR and XNOR gates. The present circuit consist optimized power intakeas well asdelay due to smallamount produced capacitance and power dissipation for low short circuit. Here we utilize 6 new hybrid 1 bit full adder circuitthat produces to and fro XOR/XNOR gates. Here the present circuit has its own advantages like rapidity, power consumption and delay in power product, dynamic capability and so on. Here we proposed signals like HSPICE, Cadence simulations for investigating the performance results which are based on 65-nm CMOS process technical models that indicate high speed and power against FA signals. So here we propose a novel new transistor sizing method that optimizes the PDP circuits. The present circuit investigates on various supply terms of variations like threshold voltages, size of transistors, input noise and output capacitance by utilizing numerical computation particle swam optimization algorithm for achieving desired value in optimum PDP with few iterations

Compact Active Quenching Circuit for Single Photon Avalanche Diodes Arrays

2017 ◽  
Vol 26 (10) ◽  
pp. 1750149
Author(s):  
Lixia Zheng ◽  
Huan Hu ◽  
Ziqing Weng ◽  
Qun Yao ◽  
Jin Wu ◽  
...  
Keyword(s):  
Power Consumption ◽  
Small Area ◽  
Single Photon ◽  
Low Power Consumption ◽  
Cmos Process ◽  
Experimental Measurements ◽  
Avalanche Diode ◽  
Avalanche Diodes ◽  
Area Occupation ◽  
Sensing Time

A compact quenching circuit for Single Photon Avalanche Diode (SPAD) arrays is presented. The proposed circuit preserves the advantages of small area occupation and low power consumption, since it mainly adopts the junction capacitance of the detector to sense the avalanche current. The sensing time is now limited more by the detector rather than the circuit itself. Fabricated in TSMC standard 0.35[Formula: see text][Formula: see text]m CMOS process, the proposed circuit only occupies an area of 20[Formula: see text][Formula: see text]m[Formula: see text][Formula: see text][Formula: see text]31[Formula: see text][Formula: see text]m and can operate properly with the detector biased up to 5[Formula: see text]V above breakdown. The circuit functionality has been verified by experimental measurements, operating with 64[Formula: see text][Formula: see text][Formula: see text]64 InGaAs/InP single photon avalanche diode arrays for time-of-flight-based applications.

scholarly journals A 6-bit Low-Power High-Speed Flash ADC using 180 nm CMOS process

2014 ◽  
Vol 17 (1) ◽  
pp. 52-61
Author(s):  
Thanh Tri Vo ◽  
Trong Tu Bui ◽  
Duc Hung Le ◽  
Cong Kha Pham
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Sampling Rate ◽  
Low Power Consumption ◽  
Cmos Process ◽  
Flash Adc ◽  
High Sampling Rate ◽  
Simulation Results

In this paper we present a design of Flash-ADC that can achieve high performance and low power consumption. By using the Double Sampling Rate technique and a new comparator topology with low kick-back noise, this design can achieve high sampling rate while still consuming low power. The design is implemented in a 0.18 m CMOS process. The simulation results show that this design can work at 400 MSps and power consumption is only 16.24 mW. The DNL and INL are 0.15 LSB and 0.6 LSB, respectively.

scholarly journals Ultracompact and low-power-consumption silicon thermo-optic switch for high-speed data

Nanophotonics ◽  
2020 ◽  
Vol 10 (2) ◽  
pp. 937-945
Author(s):  
Ruihuan Zhang ◽  
Yu He ◽  
Yong Zhang ◽  
Shaohua An ◽  
Qingming Zhu ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Pulse Amplitude ◽  
Telecommunication Networks ◽  
Low Power Consumption ◽  
Power Efficient ◽  
High Speed Data ◽  
On Chip

AbstractUltracompact and low-power-consumption optical switches are desired for high-performance telecommunication networks and data centers. Here, we demonstrate an on-chip power-efficient 2 × 2 thermo-optic switch unit by using a suspended photonic crystal nanobeam structure. A submilliwatt switching power of 0.15 mW is obtained with a tuning efficiency of 7.71 nm/mW in a compact footprint of 60 μm × 16 μm. The bandwidth of the switch is properly designed for a four-level pulse amplitude modulation signal with a 124 Gb/s raw data rate. To the best of our knowledge, the proposed switch is the most power-efficient resonator-based thermo-optic switch unit with the highest tuning efficiency and data ever reported.

scholarly journals A Low-Power 12-Bit 20 MS/s Asynchronously Controlled SAR ADC for WAVE ITS Sensor Based Applications

Sensors ◽  
2021 ◽  
Vol 21 (7) ◽  
pp. 2260
Author(s):  
Khuram Shehzad ◽  
Deeksha Verma ◽  
Danial Khan ◽  
Qurat Ul Ain ◽  
Muhammad Basim ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Intelligent Transportation System ◽  
Cmos Process ◽  
Process Technology ◽  
Back Issue ◽  
Digital To Analog Converter ◽  
Analog To Digital ◽  
Switching Method

A low power 12-bit, 20 MS/s asynchronously controlled successive approximation register (SAR) analog-to-digital converter (ADC) to be used in wireless access for vehicular environment (WAVE) intelligent transportation system (ITS) sensor based application is presented in this paper. To optimize the architecture with respect to power consumption and performance, several techniques are proposed. A switching method which employs the common mode charge recovery (CMCR) switching process is presented for capacitive digital-to-analog converter (CDAC) part to lower the switching energy. The switching technique proposed in our work consumes 56.3% less energy in comparison with conventional CMCR switching method. For high speed operation with low power consumption and to overcome the kick back issue in the comparator part, a mutated dynamic-latch comparator with cascode is implemented. In addition, to optimize the flexibility relating to the performance of logic part, an asynchronous topology is employed. The structure is fabricated in 65 nm CMOS process technology with an active area of 0.14 mm2. With a sampling frequency of 20 MS/s, the proposed architecture attains signal-to-noise distortion ratio (SNDR) of 65.44 dB at Nyquist frequency while consuming only 472.2 µW with 1 V power supply.

scholarly journals A high-speed hybrid Full Adder with low power consumption

2012 ◽  
Vol 9 (24) ◽  
pp. 1900-1905
Author(s):  
Kamran Delfan Hemmati ◽  
Mojtaba Behzad Fallahpour ◽  
Abbas Golmakani ◽  
Kamyar Delfan Hemmati
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Full Adder ◽  
Low Power Consumption

scholarly journals Novel Design of Low-Power High-Speed Hybrid Full Adder Design using Gate Diffusion Input (GDI) Technique

2020 ◽  
Vol 9 (12) ◽  
pp. 323-328
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Critical Path ◽  
Circuit Simulation ◽  
Full Adder ◽  
Cmos Process ◽  
Path Delay ◽  
Process Technology ◽  
Xnor Gate

VLSI technology become one of the most significant and demandable because of the characteristics like device portability, device size, large amount of features, expenditure, consistency, rapidity and many others. Multipliers and Adders place an important role in various digital systems such as computers, process controllers and signal processors in order to achieve high speed and low power. Two input XOR/XNOR gate and 2:1 multiplexer modules are used to design the Hybrid Full adders. The XOR/XNOR gate is the key punter of power included in the Full adder cell. However this circuit increases the delay, area and critical path delay. Hence, the optimum design of the XOR/XNOR is required to reduce the power consumption of the Full adder Cell. So a 6 New Hybrid Full adder circuits are proposed based on the Novel Full-Swing XOR/XNOR gates and a New Gate Diffusion Input (GDI) design of Full adder with high-swing outputs. The speed, power consumption, power delay product and driving capability are the merits of the each proposed circuits. This circuit simulation was carried used cadence virtuoso EDA tool. The simulation results based on the 90nm CMOS process technology model.

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