A Multi-Output Multi-String High-Efficiency WLED Driver Using 40 nm CMOS Technology

In this work, a multi-independent-output, multi-string, high-efficiency, boost-converter-based white LED (WLED) driver architecture is proposed. It utilizes a single inductor main switch with a common maximum duty cycle controller (MDCC) in the feedback loop. A simple pulse skipping controller (PSC) is utilized in each high-side switch of the multiple independent outputs. Despite the presence of multiple independent outputs, a single over-voltage protection (OVP) circuit is used at the output to protect the circuit from any voltage above 27 V. An open circuit in any of the strings is addressed, in addition to the LED’s short-circuit conditions. Excellent current matching between strings is achieved, despite the low ON-resistance (Rdson) of transistors used in the 40 nm process. Most circuits are designed in digital CMOS logic to overcome the extreme process variations in the 40 nm node. Compared to a single output parallel strings topology, a 50% improvement in efficiency is achieved relative to extremely unbalanced strings. Three strings are used in this proposal, but more strings can be supported with the same topology. Each string is driven by a 25 mA current sink. An input voltage of 3.2–4.2 V and an output voltage up to 27 V are supported.

Download Full-text

17.8%-efficient Amorphous Silicon Heterojunction Solar Cells on p-type Silicon Wafers

MRS Proceedings ◽

10.1557/proc-0910-a26-05 ◽

2006 ◽

Vol 910 ◽

Cited By ~ 2

Author(s):

Qi Wang ◽

Matt P. Page ◽

Eugene Iwancizko ◽

Yueqin Xu ◽

Yanfa Yan ◽

...

Keyword(s):

Solar Cells ◽

Solar Cell ◽

Amorphous Silicon ◽

High Efficiency ◽

Short Circuit ◽

Open Circuit ◽

Layer Growth ◽

Surface Recombination Velocity ◽

Back Contact ◽

P Type

AbstractWe have achieved an independently-confirmed 17.8% conversion efficiency in a 1-cm2, p-type, float-zone silicon (FZ-Si) based heterojunction solar cell. Both the front emitter and back contact are hydrogenated amorphous silicon (a-Si:H) deposited by hot-wire chemical vapor deposition (HWCVD). This is the highest reported efficiency for a HWCVD silicon heterojunction (SHJ) solar cell. Two main improvements lead to our most recent increases in efficiency: 1) the use of textured Si wafers, and 2) the application of a-Si:H heterojunctions on both sides of the cell. Despite the use of textured c-Si to increase the short-circuit current, we were able to maintain the same 0.65 V open-circuit voltage as on flat c-Si. This is achieved by coating a-Si:H conformally on the c-Si surfaces, including covering the tips of the anisotropically-etched pyramids. A brief atomic H treatment before emitter deposition is not necessary on the textured wafers, though it was helpful in the flat wafers. It is essential to high efficiency SHJ solar cells that the emitter grows abruptly as amorphous silicon, instead of as microcrystalline or epitaxial Si. The contact on each side of the cell comprises a thin (< 5 nm) low substrate temperature (~100°C) intrinsic a-Si:H layer, followed by a doped layer. Our intrinsic layers are deposited at 0.3-1.2 nm/s. The doped emitter and back-contact layers were deposited at a higher temperature (>200°C) and grown from PH3/SiH4/H2 and B2H6/SiH4/H2 doping gas mixtures, respectively. This combination of low (intrinsic) and high (doped layer) growth temperatures was optimized by lifetime and surface recombination velocity measurements. Our rapid efficiency advance suggests that HWCVD may have advantages over plasma-enhanced (PE) CVD in fabrication of high-efficiency heterojunction c-Si cells; there is no need for process optimization to avoid plasma damage to the delicate, high-quality, Si wafers.

Download Full-text

High-efficiency CIGS solar cell by optimization of doping concentration, thickness and energy band gap

Modern Physics Letters B ◽

10.1142/s0217984920500530 ◽

2019 ◽

Vol 34 (04) ◽

pp. 2050053

Author(s):

Fatemeh Ghavami ◽

Alireza Salehi

Keyword(s):

Solar Cell ◽

Band Gap ◽

High Efficiency ◽

Cell Structure ◽

Short Circuit ◽

Short Circuit Current ◽

Short Circuit Current Density ◽

Open Circuit ◽

Absorber Layer ◽

Window Layer

In this paper, the performance of copper-indium-gallium-diselenide Cu(In,Ga)Se2 solar cell, with ZnO window layer, ZnSe buffer layer, CIGS absorber layer and InGaP reflector layer was studied. The study was performed using the TCAD Silvaco simulator. The effects of grading the band gap of CIGS absorber layer, the various thicknesses and doping concentrations of different layers have been investigated. By optimizing the solar cell structure, we have obtained a maximum open circuit voltage of 0.91901 V, a short circuit current density of 39.89910 mA/cm2, a fill factor (FF) of 86.67040% and an efficiency of 31.78% which is much higher than the values for similar CIGS solar cells reported so far.

Download Full-text

High Performance Dye-Sensitized Solar Cells Based on Vacuum-Assisted Thermal Deposition Pt Counter Electrodes

Key Engineering Materials ◽

10.4028/www.scientific.net/kem.602-603.866 ◽

2014 ◽

Vol 602-603 ◽

pp. 866-870

Author(s):

Yan Xiang Wang ◽

He Dong Jiang ◽

Jian Sun

Keyword(s):

High Performance ◽

High Efficiency ◽

Electrochemical Impedance ◽

Short Circuit ◽

Dye Sensitized Solar Cells ◽

Open Circuit ◽

Counter Electrodes ◽

Thermal Deposition ◽

Dye Sensitized ◽

Loading Amount

In this work, the vacuum-assisted thermal deposition platinum (Pt) film was prepared and used as a counter electrode (CE) in dye sensitized solar cell (DSC). The films were characterized by scanning electron microscopy (SEM). Electrochemical catalytic activities of the films were also characterized by cyclic voltammetry (CV) and electrochemical impedance spectroscopy (EIS). The effects of the Pt loading amount on the fluorine-doped tin oxide (FTO) glass and titration time on the performance of the DSC were investigated. The optimal performance of the DSC was obtained when using the three-time titration with 1.69 mg/cm2 Pt loading amount vacuum-assisted thermal deposit CE. The DSC showed a high efficiency of 7.20%. The short-circuit current density (Jsc), open circuit voltage (Voc) and fill factor (FF) were 13.79 mA·cm-2, 0.73 V and 0.71, respectively.

Download Full-text

Simulation of InAIN/Si Single-Heterojunction Solar Cells Using wxAMPS

Applied Mechanics and Materials ◽

10.4028/www.scientific.net/amm.665.111 ◽

2014 ◽

Vol 665 ◽

pp. 111-114 ◽

Cited By ~ 1

Author(s):

Ying Huang ◽

Xiao Ming Shen ◽

Xiao Feng Wei

Keyword(s):

Solar Cells ◽

Fill Factor ◽

High Efficiency ◽

Open Circuit Voltage ◽

Short Circuit ◽

Short Circuit Current ◽

Indium Content ◽

Open Circuit ◽

Heterojunction Solar Cells ◽

Si Solar Cells

In this paper, InAlN/Si single-heterojunction solar cells have been theoretically simulated based on wxAMPS software. The photovoltaic parameters, such as open circuit voltage, short circuit current, fill factor and conversion efficiency were investigated with changing the indium content and thickness of n-InAlN layer. Simulation results show that the optimum efficiency of InAlN/Si solar cells is 23.1% under AM 1.5G spectral illuminations, with the indium content and thickness of n-InAlN layer are 0.65 and 600nm, respectively. The simulation would contribute to design and fabricate high efficiency InAlN/Si solar cells in experiment.

Download Full-text

Investigation of Low-Cost Surface Processing Techniques for Large-Size Multicrystalline Silicon Solar Cells

International Journal of Photoenergy ◽

10.1155/2010/268035 ◽

2010 ◽

Vol 2010 ◽

pp. 1-6 ◽

Cited By ~ 10

Author(s):

Yuang-Tung Cheng ◽

Jyh-Jier Ho ◽

William J. Lee ◽

Song-Yeu Tsai ◽

Yung-An Lu ◽

...

Keyword(s):

Solar Cells ◽

Silicon Nitride ◽

Conversion Efficiency ◽

High Efficiency ◽

Short Circuit ◽

Open Circuit ◽

Multicrystalline Silicon ◽

Double Layers ◽

Large Size ◽

Si Solar Cells

The subject of the present work is to develop a simple and effective method of enhancing conversion efficiency in large-size solar cells using multicrystalline silicon (mc-Si) wafer. In this work, industrial-type mc-Si solar cells with area of125×125 mm2were acid etched to produce simultaneouslyPOCl3emitters and silicon nitride deposition by plasma-enhanced chemical vapor deposited (PECVD). The study of surface morphology and reflectivity of different mc-Si etched surfaces has also been discussed in this research. Using our optimal acid etching solution ratio, we are able to fabricate mc-Si solar cells of 16.34% conversion efficiency with double layers silicon nitride (Si3N4) coating. From our experiment, we find that depositing double layers silicon nitride coating on mc-Si solar cells can get the optimal performance parameters. Open circuit (Voc) is 616 mV, short circuit current (Jsc) is 34.1 mA/cm2, and minority carrier diffusion length is 474.16 μm. The isotropic texturing and silicon nitride layers coating approach contribute to lowering cost and achieving high efficiency in mass production.

Download Full-text

Controlled Photoanode Properties for Large-Area Efficient and Stable Dye-Sensitized Photovoltaic Modules

Nanomaterials ◽

10.3390/nano11082125 ◽

2021 ◽

Vol 11 (8) ◽

pp. 2125

Author(s):

Wei-Hao Chiu ◽

Kun-Mu Lee ◽

Vembu Suryanarayanan ◽

Jen-Fu Hsu ◽

Ming-Chung Wu

Keyword(s):

High Efficiency ◽

Short Circuit ◽

Short Circuit Current ◽

Solution Concentration ◽

Short Circuit Current Density ◽

Open Circuit ◽

Tio2 Electrode ◽

Large Area ◽

Dye Sensitized ◽

Module Efficiency

Nowadays, a dye-sensitized solar cell (DSSC) attracts attention to its development widely due to its several advantages, such as simple processes, low costs, and flexibility. In this work, we demonstrate the difference in device structures between small size and large size cells (5 cm × 5 cm, 10 cm × 10 cm and 10 cm × 15 cm). The design of the photoanode and dye-sensitized process plays important roles in affecting the cell efficiency and stability. The effects of the TiO2 electrode, using TiCl4(aq) pretreatment and post-treatment processes, are also discussed, whereas, the open-circuit voltage (Voc), short-circuit current density (Jsc), and module efficiency are successfully improved. Furthermore, the effects on module performances by some factors, such as dye solution concentration, dye soaking temperature, and electrolyte injection method are also investigated. We have demonstrated that the output power of a 5 cm × 5 cm DSSC module increases from 86.2 mW to 93.7 mW, and the module efficiency achieves an outstanding performance of 9.79%. Furthermore, enlarging the DSSC modules to two sizes (10 cm × 10 cm and 10 cm × 15 cm) and comparing the performance with different module designs (C-DSSC and S-DSSC) also provides the specific application of polymer sealing and preparing high-efficiency large-area DSSC modules.

Download Full-text

Design of Silicon Nanowire Array for PEDOT:PSS-Silicon Nanowire-Based Hybrid Solar Cell

Energies ◽

10.3390/en13153797 ◽

2020 ◽

Vol 13 (15) ◽

pp. 3797 ◽

Cited By ~ 1

Author(s):

Syed Abdul Moiz ◽

A. N. M. Alahmadi ◽

Abdulah Jeza Aljohani

Keyword(s):

Solar Cell ◽

High Efficiency ◽

Short Circuit ◽

Silicon Nanowire ◽

Nanowire Array ◽

Short Circuit Current ◽

Open Circuit ◽

Hybrid Solar Cell ◽

Design Issues ◽

Sinw Array

Among various photovoltaic devices, the poly 3, 4-ethylenedioxythiophene:poly styrenesulfonate (PEDOT:PSS) and silicon nanowire (SiNW)-based hybrid solar cell is getting momentum for the next generation solar cell. Although, the power-conversion efficiency of the PEDOT:PSS–SiNW hybrid solar cell has already been reported above 13% by many researchers, it is still at a primitive stage and requires comprehensive research and developments. When SiNWs interact with conjugate polymer PEDOT:PSS, the various aspects of SiNW array are required to optimize for high efficiency hybrid solar cell. Therefore, the designing of silicon nanowire (SiNW) array is a crucial aspect for an efficient PEDOT:PSS–SiNW hybrid solar cell, where PEDOT:PSS plays a role as a conductor with an transparent optical window just-like as metal-semiconductor Schottky solar cell. This short review mainly focuses on the current research trends for the general, electrical, optical and photovoltaic design issues associated with SiNW array for PEDOT:PSS–SiNW hybrid solar cells. The foremost features including the morphology, surface traps, doping of SiNW, which limit the efficiency of the PEDOT:PSS–SiNW hybrid solar cell, will be addressed and reviewed. Finally, the SiNW design issues for boosting up the fill-factor, short-circuit current and open-circuit voltage will be highlighted and discussed.

Download Full-text

High-Efficiency HIT Solar Cells for Excellent Power Generating Properties

MRS Proceedings ◽

10.1557/proc-1123-1123-p03-01 ◽

2008 ◽

Vol 1123 ◽

Author(s):

Toshihiro Kinoshita ◽

Daisuke Ide ◽

Yasufumi Tsunomura ◽

Shigeharu Taira ◽

Toshiaki Baba ◽

...

Keyword(s):

Solar Cells ◽

Solar Cell ◽

Conversion Efficiency ◽

Production Cost ◽

High Efficiency ◽

Open Circuit Voltage ◽

Short Circuit ◽

Open Circuit ◽

Surface Recombination Velocity ◽

Dominant Factor

AbstractIn order to achieve the widespread use of HIT (Hetero-junction with I etero-Intrinsic T ntrinsic Thin-layer) solar cells, it is important to reduce the power generating cost. There are three main approaches for reducing this cost: raising the conversion efficiency of the HIT cell, using a thinner wafer to reduce the wafer cost, and raising the open circuit voltage to obtain a better temperature coefficient. With the first approach, we have achieved the highest conversion efficiency values of 22.3%, confirmed by AIST, in a HIT solar cell. This cell has an open circuit voltage of 0.725 V, a short circuit current density of 38.9 mA/cm2 and a fill factor of 0.791, with a cell size of 100.5 cm2. The second approach is to use thinner Si wafers. The shortage of Si feedstock and the strong requirement of a lower sales price make it necessary for solar cell manufacturers to reduce their production cost. The wafer cost is an especially dominant factor in the production cost. In order to provide low-priced, high-quality solar cells, we are trying to use thinner wafers. We obtained a conversion efficiency of 21.4% (measured by Sanyo) for a HIT solar cell with a thickness of 85μm. Even better, there was absolutely no sagging in our HIT solar cell because of its symmetrical structure. The third approach is to raise the open circuit voltage. We obtained a remarkably higher Voc of 0.739 V with the thinner cell mentioned above because of its low surface recombination velocity. The high Voc results in good temperature properties, which allow it to generate a large amount of electricity at high temperatures.

Download Full-text

Effect of CdTe thickness reduction in high efficiency CdS/CdTe solar cells

MRS Proceedings ◽

10.1557/proc-668-h6.4 ◽

2001 ◽

Vol 668 ◽

Cited By ~ 8

Author(s):

Akhlesh Gupta ◽

I. Matulionis ◽

J. Drayton ◽

A.D. Compaan

Keyword(s):

Solar Cells ◽

High Efficiency ◽

Short Circuit ◽

Short Circuit Current ◽

Cdte Film ◽

Open Circuit ◽

Thickness Reduction ◽

X Ray Diffraction ◽

Cell Parameters ◽

Cdte Solar Cells

ABSTRACTHigh efficiency CdTe solar cells are typically grown with CdTe thicknesses from 3 to 15 μm, although the thickness required for 90% absorption of the incident irradiation at 800 nm is only ∼1 μm. In this paper, we present the effect of CdTe thickness reduction on the performance of CdS/CdTe solar cells in which both the CdS and CdTe films were grown by sputtering. We produced a series of cells with different CdTe thickness (from 0.5 to 3.0 μm), and held the CdS thickness and back-contact-processing constant. The effect of CdTe thickness reduction on the diffusion of CdS into CdTe was studied using optical absorption and x-ray diffraction techniques. Only slight decreases occur in open-circuit voltage, short-circuit current, and fill factor with decrease in CdTe film thickness to 1.0 μm. Almost 10% efficient cells were obtained with 1 μm CdTe. Below 1 μm, all cell parameters decrease more rapidly, including the red quantum efficiency.

Download Full-text

Graded Carrier Concentration Absorber Profile for High Efficiency CIGS Solar Cells

International Journal of Photoenergy ◽

10.1155/2015/410549 ◽

2015 ◽

Vol 2015 ◽

pp. 1-9 ◽

Cited By ~ 17

Author(s):

Antonino Parisi ◽

Riccardo Pernice ◽

Vincenzo Rocca ◽

Luciano Curcio ◽

Salvatore Stivala ◽

...

Keyword(s):

Solar Cells ◽

Band Gap ◽

Carrier Concentration ◽

High Efficiency ◽

Energy Gap ◽

Short Circuit ◽

Short Circuit Current ◽

Open Circuit ◽

Doping Density ◽

Cigs Solar Cells

We demonstrate an innovative CIGS-based solar cells model with a graded doping concentration absorber profile, capable of achieving high efficiency values. In detail, we start with an in-depth discussion concerning the parametrical study of conventional CIGS solar cells structures. We have used the wxAMPS software in order to numerically simulate cell electrical behaviour. By means of simulations, we have studied the variation of relevant physical and chemical parameters—characteristic of such devices—with changing energy gap and doping density of the absorber layer. Our results show that, in uniform CIGS cell, the efficiency, the open circuit voltage, and short circuit current heavily depend on CIGS band gap. Our numerical analysis highlights that the band gap value of 1.40 eV is optimal, but both the presence of Molybdenum back contact and the high carrier recombination near the junction noticeably reduce the crucial electrical parameters. For the above-mentioned reasons, we have demonstrated that the efficiency obtained by conventional CIGS cells is lower if compared to the values reached by our proposed graded carrier concentration profile structures (up to 21%).

Download Full-text