scholarly journals CORDIC Hardware Acceleration Using DMA-Based ISA Extension

2022 ◽  
Vol 12 (1) ◽  
pp. 4
Author(s):  
Erez Manor ◽  
Avrech Ben-David ◽  
Shlomo Greenberg
Keyword(s):  
Low Power ◽  
High Performance ◽  
Low Cost ◽  
Hardware Acceleration ◽  
Embedded Processors ◽  
Data Path ◽  
Instruction Set ◽  
Mathematical Functions ◽  
Coordinate Rotation ◽  
Software Implementations

The use of RISC-based embedded processors aimed at low cost and low power is becoming an increasingly popular ecosystem for both hardware and software development. High-performance yet low-power embedded processors may be attained via the use of hardware acceleration and Instruction Set Architecture (ISA) extension. Recent publications of AI have demonstrated the use of Coordinate Rotation Digital Computer (CORDIC) as a dedicated low-power solution for solving nonlinear equations applied to Neural Networks (NN). This paper proposes ISA extension to support floating-point CORDIC, providing efficient hardware acceleration for mathematical functions. A new DMA-based ISA extension approach integrated with a pipeline CORDIC accelerator is proposed. The CORDIC ISA extension is directly interfaced with a standard processor data path, allowing efficient implementation of new trigonometric ALU-based custom instructions. The proposed DMA-based CORDIC accelerator can also be used to perform repeated array calculations, offering a significant speedup over software implementations. The proposed accelerator is evaluated on Intel Cyclone-IV FPGA as an extension to Nios processor. Experimental results show a significant speedup of over three orders of magnitude compared with software implementation, while applied to trigonometric arrays, and outperforms the existing commercial CORDIC hardware accelerator.

scholarly journals A High-Performance Parallel FDTD Method Enhanced by Using SSE Instruction Set

2012 ◽  
Vol 2012 ◽  
pp. 1-10 ◽  
Author(s):  
Dau-Chyrh Chang ◽  
Lihong Zhang ◽  
Xiaoling Yang ◽  
Shao-Hsiang Yen ◽  
Wenhua Yu
Keyword(s):  
High Performance ◽  
Fdtd Method ◽  
Hardware Acceleration ◽  
Single Instruction Multiple Data ◽  
Instruction Set ◽  
Computer Cluster ◽  
Simulation Performance ◽  
Acceleration Technique ◽  
Multiple Data ◽  
Difference Time

We introduce a hardware acceleration technique for the parallel finite difference time domain (FDTD) method using the SSE (streaming (single instruction multiple data) SIMD extensions) instruction set. The implementation of SSE instruction set to parallel FDTD method has achieved the significant improvement on the simulation performance. The benchmarks of the SSE acceleration on both the multi-CPU workstation and computer cluster have demonstrated the advantages of (vector arithmetic logic unit) VALU acceleration over GPU acceleration. Several engineering applications are employed to demonstrate the performance of parallel FDTD method enhanced by SSE instruction set.

LP-NUCA: Networks-in-Cache for High-Performance Low-Power Embedded Processors

2012 ◽  
Vol 20 (8) ◽  
pp. 1510-1523 ◽  
Author(s):  
Darío Suárez Gracia ◽  
Giorgos Dimitrakopoulos ◽  
Teresa Monreal Arnal ◽  
Manolis G. H. Katevenis ◽  
Víctor Viñals Yufera
Keyword(s):  
Low Power ◽  
High Performance ◽  
Embedded Processors

Thermal-Enhanced and Cost-Effective 3D IC Integration With TSV (Through-Silicon Via) Interposers for High-Performance Applications

2010 ◽  
Author(s):  
John H. Lau ◽  
Y. S. Chan ◽  
S. W. Ricky Lee
Keyword(s):  
Low Power ◽  
High Power ◽  
Heat Sink ◽  
High Performance ◽  
Low Cost ◽  
Bottom Surface ◽  
Heat Spreader ◽  
Creep Theory ◽  
Integration System ◽  
3D Ic

A low-cost (with bare chips) and high (electrical, thermal, and mechanical) performance 3D IC integration system-in-package (SiP) is designed and described. This system consists of a silicon interposer with through-silicon vias (TSV) [1–24] and redistribution layers (RDL), which carries the high-power flip chips with microbumps on its top surface and the low-power chips at its bottom surface. TSVs in the high- and low-power chips are optional but should be avoided. The backside of the high-power chips is attached to a heat spreader with or w/o a heat sink. This 3D IC integration system is supported (packaged) by a simple conventional organic substrate. The heat spreader (with or w/o heat sink) and the substrate are connected by a ring stiffener, which provides adequate standoff for the 3D IC integration system. This novel structural design offers potential solutions for high-power, high-performance, high pin-count, ultra fine-pitch, small real-estate, and low-cost applications. Thermal management and reliability of the proposed systems are demonstrated by simulations based on heat-transfer theory and time and temperature dependent creep theory.

A novel low cost roll-to-roll manufacturing compatible ultra-thin chip integration and direct metal interconnection process for flexible hybrid electronics

2019 ◽  
Vol 2019 (NOR) ◽  
pp. 000006-000011
Author(s):  
N Palavesam ◽  
W Hell ◽  
A Drost ◽  
C Landesberger ◽  
C Kutter ◽  
...  
Keyword(s):  
Low Power ◽  
Organic Electronics ◽  
High Performance ◽  
Low Cost ◽  
Physical Object ◽  
Successful Implementation ◽  
Electrical Measurements ◽  
Sensors And Actuators ◽  
Human Machine Interaction ◽  
Roll To Roll

Abstract The emerging Internet-of-Everything (IoE) framework aims to revolutionise human-machine interaction where billions of sensors and actuators placed on almost every physical object will be tasked to communicate with each other. A substantial fraction of these devices will be placed on locations that would undergo repeated bending deformation (such as sensors for prosthetics, human body and robots) or on curved surfaces (like interior as well as exterior of automobiles, buildings and industrial equipment). Therefore, flexible sensors and actuators delivering high performance at low power requirements and manufactured at low cost will be the key for successful implementation of IoE. Though massive developments achieved in printed and organic electronics have enabled them to fulfil the required flexibility and low cost demands of IoE applications, printed and organic electronics often fall short of the high performance and low power requirements demonstrated by silicon ICs. Flexible chip foil packages fabricated by integrating ultra-thin bare silicon ICs fulfil the aforementioned demands posed by IoE applications and therefore, they are often considered as potential enablers of IoE. Here, we present an innovative roll-to-roll manufacturing compatible low cost approach for direct metal interconnection and integration of ultra-thin silicon ICs. The thickness of the fabricated flexible packages with the integrated and interconnected ultra-thin ICs were as thin as 100 μm. Electrical measurements conducted on the 60 fabricated samples with interconnected flexible ultra-thin ICs revealed a very promising yield of 94%.

An Overview of Multichip Module Technology for low Power Applications

1992 ◽  
Vol 264 ◽  
Author(s):  
Chung W. Ho ◽  
Sharon McAfee-Hunter
Keyword(s):  
Thin Film ◽  
Low Power ◽  
Manufacturing Process ◽  
High Performance ◽  
Low Cost ◽  
High Density ◽  
Point Of View ◽  
Multichip Module ◽  
Multichip Modules

AbstractThin-film multichip modules (i.e. MCM-D) can provide simple, low-cost packaging and interconnect options for interconnecting high-density, high-performance devices. The following is an overview of an MCM-D technology that can be implemented on top of several substrate materials. Tradeoffs will be discussed related to using different substrate materials and the corresponding implications from the assembly point of view. The MCM-D manufacturing process is reviewed and the subsequent reliability results are discussed.

Design of Velocity Measuring System of Car Based on MCU

2013 ◽  
Vol 373-375 ◽  
pp. 363-366
Author(s):  
Jing Sheng Yu ◽  
Hong Qiang Sun
Keyword(s):  
Mathematical Model ◽  
Power Consumption ◽  
Low Power ◽  
Control Systems ◽  
Basic Principle ◽  
High Performance ◽  
Low Cost ◽  
Measuring System ◽  
Low Power Consumption ◽  
Velocity Measuring

It describes the basic principle of velocity parameters measuring of car in operation, establishes the related mathematical model. It disigns an intelligent, integrated digital solutions to combination instrumentation of the car based on MC9S12DP256B. This system has advantages of high performance, high precision, low cost, low power consumption, good stability, sensitive respond and expandability. The system measures and shows online velocity parameters of the car. It has fuction such as safety alarm. The system reserves bus interface such as SCI and CAN, correspondences easily with other electronic engine control systems of the car.

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