A Survey of Software-Defined Networks-on-Chip: Motivations, Challenges and Opportunities

Current computing platforms encourage the integration of thousands of processing cores, and their interconnections, into a single chip. Mobile smartphones, IoT, embedded devices, desktops, and data centers use Many-Core Systems-on-Chip (SoCs) to exploit their compute power and parallelism to meet the dynamic workload requirements. Networks-on-Chip (NoCs) lead to scalable connectivity for diverse applications with distinct traffic patterns and data dependencies. However, when the system executes various applications in traditional NoCs—optimized and fixed at synthesis time—the interconnection nonconformity with the different applications’ requirements generates limitations in the performance. In the literature, NoC designs embraced the Software-Defined Networking (SDN) strategy to evolve into an adaptable interconnection solution for future chips. However, the works surveyed implement a partial Software-Defined Network-on-Chip (SDNoC) approach, leaving aside the SDN layered architecture that brings interoperability in conventional networking. This paper explores the SDNoC literature and classifies it regarding the desired SDN features that each work presents. Then, we described the challenges and opportunities detected from the literature survey. Moreover, we explain the motivation for an SDNoC approach, and we expose both SDN and SDNoC concepts and architectures. We observe that works in the literature employed an uncomplete layered SDNoC approach. This fact creates various fertile areas in the SDNoC architecture where researchers may contribute to Many-Core SoCs designs.

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Near-Optimal Thermal Monitoring Framework for Many-Core Systems-on-Chip

IEEE Transactions on Computers ◽

10.1109/tc.2015.2395423 ◽

2015 ◽

Vol 64 (11) ◽

pp. 3197-3209 ◽

Cited By ~ 2

Author(s):

Juri Ranieri ◽

Alessandro Vincenzi ◽

Amina Chebira ◽

David Atienza ◽

Martin Vetterli

Keyword(s):

Thermal Monitoring ◽

Systems On Chip ◽

Monitoring Framework ◽

On Chip ◽

Many Core

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MCVP-NoC: Many-Core Virtual Platform with Networks-on-Chip support

2013 IEEE 10th International Conference on ASIC ◽

10.1109/asicon.2013.6811836 ◽

2013 ◽

Author(s):

Dexue Zhang ◽

Xiaoyang Zeng ◽

Zongyan Wang ◽

Weike Wang ◽

Xinhua Chen

Keyword(s):

Networks On Chip ◽

Virtual Platform ◽

On Chip ◽

Many Core

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FoToNoC: A Folded Torus-Like Network-on-Chip Based Many-Core Systems-on-Chip in the Dark Silicon Era

IEEE Transactions on Parallel and Distributed Systems ◽

10.1109/tpds.2016.2643669 ◽

2017 ◽

Vol 28 (7) ◽

pp. 1905-1918 ◽

Cited By ~ 16

Author(s):

Lei Yang ◽

Weichen Liu ◽

Weiwen Jiang ◽

Mengquan Li ◽

Peng Chen ◽

...

Keyword(s):

Network On Chip ◽

Dark Silicon ◽

Systems On Chip ◽

On Chip ◽

Many Core

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Diseño e Implementación de un Multiprocessor Systems-on-Chip (MPSoC) Interconectado por una Networks-on-Chip (NoC)

MASKAY ◽

10.24133/maskay.v3i1.129 ◽

2013 ◽

Vol 3 (1) ◽

pp. 40

Author(s):

Wilson Mauricio Chicaiza ◽

Daniel Gonzalo Verdesoto

Keyword(s):

Multiprocessor Systems ◽

Networks On Chip ◽

Systems On Chip ◽

On Chip ◽

Medios De Comunicacion

En el presente documento se presenta una breve caracterización de los medios de comunicación empleados en arquitecturas multiprocesadas. Esta caracterización tiene como objetivo principal el mostrar un nuevo modelo de comunicación basado en conmutación de paquetes a los cuales se les denomina como Networks-On-Chip (NoC). Esta publicación muestra una arquitectura de red llamada NoC Hermes, la cual fue interconectada a un Multiprocessor-Systems-on-Chip (MPSoC) compuesto de cuatro procesadores MicroBlaze. Está conexión se la realizó gracias al diseño y desarrollo de una Interfaz de Red generada en código VHDL. Por medio de la Interfaz de Red se consiguió que los procesadores MicroBlaze interactúen con los Switches de Hermes a fin de crear una arquitectura multiprocesada interconectada por una NoC. Con el motivo de realizar comparaciones también se creó otra arquitectura de multiprocesadores interconectados por buses. Para ambas arquitecturas se desarrolló una aplicación de Esteganografía enla que existe multiprocesamiento de dos procesadores trabajando simultáneamente. Lamentablemente sobre dicha aplicación no fue posible medir directamente la latencia y el consumo de energía, razón por la cual se utilizó simuladores que permitieron estimar dichas mediciones.

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3D optical networks-on-chip (NoC) for multiprocessor systems-on-chip (MPSoC)

2009 IEEE International Conference on 3D System Integration ◽

10.1109/3dic.2009.5306588 ◽

2009 ◽

Cited By ~ 20

Author(s):

Yaoyao Ye ◽

Lian Duan ◽

Jiang Xu ◽

Jin Ouyang ◽

Mo Kwai Hung ◽

...

Keyword(s):

Optical Networks ◽

Multiprocessor Systems ◽

Networks On Chip ◽

Systems On Chip ◽

On Chip

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Dynamically Reconfigurable Networks-on-Chip Using Runtime Adaptive Routers

Dynamic Reconfigurable Network-on-Chip Design ◽

10.4018/978-1-61520-807-4.ch002 ◽

2010 ◽

pp. 28-66 ◽

Cited By ~ 1

Author(s):

Mário P. Véstias ◽

Horácio C. Neto

Keyword(s):

Quality Of Service ◽

Power Consumption ◽

First Generation ◽

Networks On Chip ◽

Dynamically Reconfigurable ◽

Systems On Chip ◽

High Bandwidth ◽

Area Occupation ◽

On Chip

The recent advances in IC technology have made it possible to implement systems with dozens or even hundreds of cores in a single chip. With such a large number of cores communicating with each other there is a strong pressure over the communication infrastructure to deliver high bandwidth, low latency, low power consumption and quality of service to guarantee real-time functionality. Networks-on-Chip are definitely becoming the only acceptable interconnection structure for today’s multiprocessor systems-on-chip (MPSoC). The first generation of NoC solutions considers a regular topology, typically a 2D mesh. Routers and network interfaces are mainly homogeneous so that they can be easily scaled up and modular design is facilitated. All advantages of a NoC infrastructure were proved with this first generation of NoC solutions. However, NoCs have a relative area and speed overhead. Application specific systems can benefit from heterogeneous communication infrastructures providing high bandwidth in a localized fashion where it is needed with improved area. The efficiency of both homogeneous and heterogeneous solutions can be improved if runtime changes are considered. Dynamically or runtime reconfigurable NoCs are the second generation of NoCs since they represent a new set of benefits in terms of area overhead, performance, power consumption, fault tolerance and quality of service compared to the previous generation where the architecture is decided at design time. This chapter discusses the static and runtime customization of routers and presents results with networks-on-chip with static and adaptive routers. Runtime adaptive techniques are analyzed and compared to each other in terms of area occupation and performance. The results and the discussion presented in this chapter show that dynamically adaptive routers are fundamental in the design of NoCs to satisfy the requirements of today’s systems-on-chip.

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