scholarly journals A High-Multi Target Resolution Focal Plane Array-Based Laser Detection and Ranging Sensor

Sensors ◽  
2019 ◽  
Vol 19 (5) ◽  
pp. 1210 ◽  
Author(s):  
Hyeon-June Kim ◽  
Eun-Gyu Lee ◽  
Choul-Young Kim
Keyword(s):  
Digital Signal Processor ◽  
Focal Plane ◽  
Digital Signal ◽  
Focal Plane Array ◽  
Cmos Process ◽  
Detection Scheme ◽  
Laser Detection ◽  
Noise Current ◽  
Laser Detection And Ranging ◽  
Single Receiver

This paper introduces a digital-assisted multiple echo detection scheme, which utilizes the waste time of the full serial data readout period in a focal plane array (FPA)-based laser detection and ranging (LADAR) receiver. With the support of an external digital signal processor (DSP) and additional analog memory inserted into the receiver, the proposed readout scheme can effectively enhance multi-target resolution (MTR) three times higher than the conventional FPA-based LADAR, while maintaining low power consumption and a small area. A prototype chip was fabricated in a 0.18-μm CMOS process with an 8 × 8 FPA configuration, where each single receiver pixel occupied an area of 100 μm × 100 μm. The single receiver achieved an MTR of 20 ns with 7.47 mW power dissipation, an input referred noise current of 4.48 pA/√Hz with a bandwidth 530 MHz, a minimum detectable signal (MDS) of 340 nA, a maximum walk error of 2.2 ns, and a maximum non-linearity of 0.05% among the captured multiple echo images.

New MCT focal plane array IR detection modules and digital signal processing technologies at AIM

2000 ◽  
Author(s):  
Wolfgang A. Cabanski ◽  
Rainer Breiter ◽  
Karl-Heinz Mauk ◽  
Werner Rode ◽  
Richard Wollrab ◽  
...  
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
Focal Plane ◽  
Digital Signal ◽  
Focal Plane Array ◽  
Processing Technologies ◽  
Ir Detection

A 0.65 THz Focal-Plane Array in a Quarter-Micron CMOS Process Technology

2009 ◽  
Vol 44 (7) ◽  
pp. 1968-1976 ◽  
Author(s):  
Erik Ojefors ◽  
Ullrich R. Pfeiffer ◽  
Alvydas Lisauskas ◽  
Hartmut G. Roskos
Keyword(s):  
Focal Plane ◽  
Focal Plane Array ◽  
Cmos Process ◽  
Process Technology

Digital Signal Processing for Open-Loop Fiber-Optic Gyroscope

2011 ◽  
Vol 291-294 ◽  
pp. 2671-2675
Author(s):  
Wei Zhang ◽  
Yu Zhong Chen ◽  
Zhang Qi Song ◽  
Ming Ye Yang
Keyword(s):  
Digital Signal Processor ◽  
Fiber Optic ◽  
Detection System ◽  
Digital Signal ◽  
Open Loop ◽  
Fiber Optic Gyroscope ◽  
Detection Scheme ◽  
Field Programmable ◽  
Implementation Scheme ◽  
Rate Calculation

Digital open-loop fiber-optic gyroscope detection scheme based on sinusoidal phase modulation is introduced. A novel implementation of the detection scheme is developed with digital signal processor (DSP) and field programmable gate array (FPGA). The design and implementation of the detection system are discussed. Timing control and open-loop signal preprocessing are realized in FPGA. Rotation rate calculation is finished in DSP. Experiments result shows that good performances have been achieved and the implementation scheme is of great practical value.

scholarly journals Developing a Focal Plane Array at the GBT for 21 cm Astronomy

2012 ◽  
Author(s):  
Christopher Anderson
Keyword(s):  
Data Collection ◽  
West Virginia ◽  
Focal Plane ◽  
Focal Plane Array ◽  
Valuable Resource ◽  
Frequency Range ◽  
Intensity Mapping ◽  
Receiver Array ◽  
Green Bank Telescope ◽  
Single Receiver

Progress has been made on the design of a 9 receiver array in the 700 to 945 MHz range to replace the single receiver in that frequency range currently in use at the Green Bank Telescope (GBT) in West Virginia. The new array will increase the rate of data collection ~9x in ongoing 21 cm intensity mapping, and it should also be a valuable resource for other users of the GBT. The following paper describes the science of 21 cm intensity mapping and the work that has been done in designing the receiver for the focal plane array. 

Yield Enhancement Study: Process Variation and Design Margins Leading to Timing Issues in the RAM

2000 ◽  
Author(s):  
Srikanth Perungulam ◽  
Scott Wills ◽  
Greg Mekras
Keyword(s):  
Cross Sections ◽  
Digital Signal Processor ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Random Access ◽  
Digital Signal ◽  
Yield Enhancement ◽  
Final Conclusion ◽  
Stage Separation ◽  
Study Process

Abstract This paper illustrates a yield enhancement effort on a Digital Signal Processor (DSP) where random columns in the Static Random Access Memory (SRAM) were found to be failing. In this SRAM circuit, sense amps are designed with a two-stage separation and latch sequence. In the failing devices the bit line and bit_bar line were not separated far enough in voltage before latching got triggered. The design team determined that the sense amp was being turned on too quickly. The final conclusion was that a marginal sense amp design, combined with process deviations, would result in this type of failure. The possible process issues were narrowed to variations of via resistances on the bit and bit_bar lines. Scanning Electron Microscope (SEM) inspection of the the Focused Ion Beam (FIB) cross sections followed by Transmission Electron Microscopy (TEM) showed the presence of contaminants at the bottom of the vias causing resistance variations.

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