scholarly journals Design of a Capacitance-to-Digital Converter Based on Iterative Delay-Chain Discharge in 180 nm CMOS Technology

Sensors ◽  
2021 ◽  
Vol 22 (1) ◽  
pp. 121
Author(s):  
Mattia Cicalini ◽  
Massimo Piotto ◽  
Paolo Bruschi ◽  
Michele Dei
Keyword(s):  
Cmos Technology ◽  
Maximum Temperature ◽  
Cmos Process ◽  
Digital Converter ◽  
Ultra Low Power ◽  
Silicon Area ◽  
Trade Offs ◽  
Monitoring Applications ◽  
Linearity Error ◽  
Energy Constrained

The design of advanced miniaturized ultra-low power interfaces for sensors is extremely important for energy-constrained monitoring applications, such as wearable, ingestible and implantable devices used in the health and medical field. Capacitive sensors, together with their correspondent digital-output readout interfaces, make no exception. Here, we analyse and design a capacitance-to-digital converter, based on the recently introduced iterative delay-chain discharge architecture, showing the circuit inner operating principles and the correspondent design trade-offs. A complete design case, implemented in a commercial 180 nm CMOS process, operating at 0.9 V supply for a 0–250 pF input capacitance range, is presented. The circuit, tested by means of detailed electrical simulations, shows ultra-low energy consumption (≤1.884 nJ/conversion), excellent linearity (linearity error 15.26 ppm), good robustness against process and temperature corners (conversion gain sensitivity to process corners variation of 114.0 ppm and maximum temperature sensitivity of 81.9 ppm/∘C in the −40 ∘C, +125 ∘C interval) and medium-low resolution of 10.3 effective number of bits, while using only 0.0192 mm2 of silicon area and employing 2.93 ms for a single conversion.

A 16.4 nW, Sub-1 V, Resistor-Less Voltage Reference with BJT Voltage Divider

2018 ◽  
Vol 27 (13) ◽  
pp. 1850206 ◽  
Author(s):  
Qingshan Yang ◽  
Peiqing Han ◽  
Niansong Mei ◽  
Zhaofeng Zhang
Keyword(s):  
Low Voltage ◽  
Supply Voltage ◽  
Voltage Divider ◽  
Total Power ◽  
Cmos Process ◽  
Operating Voltage ◽  
Voltage Reference ◽  
Ultra Low Power ◽  
Silicon Area ◽  
Total Power Consumption

A 16.4[Formula: see text]nW, sub-1[Formula: see text]V voltage reference for ultra-low power low voltage applications is proposed. This design reduces the operating voltage to 0.8[Formula: see text]V by a BJT voltage divider and decreases the silicon area considerably by eliminating resistors. The PTAT and CTAT are based on SCM structures and a scaled-down [Formula: see text], respectively, to improve the process insensitivity. This work is fabricated in 0.18[Formula: see text][Formula: see text]m CMOS process with a total area of 0.0033[Formula: see text]mm2. Measured results show that it works properly for supply voltage from 0.8[Formula: see text]V to 2[Formula: see text]V. The reference voltage is 467.2[Formula: see text]mV with standard deviation ([Formula: see text]) being 12.2 mV and measured TC at best is 38.7[Formula: see text]ppm/[Formula: see text]C ranging from [Formula: see text]C to 60[Formula: see text]C. The total power consumption is 16.4[Formula: see text]nW under the minimum supply voltage at 27[Formula: see text]C.

Design Methodology of Ultra-Low-Power LC-VCOs for IoT Applications

2019 ◽  
Vol 28 (07) ◽  
pp. 1950122 ◽  
Author(s):  
Imen Ghorbel ◽  
Fayrouz Haddad ◽  
Wenceslas Rahajandraibe ◽  
Mourad Loulou
Keyword(s):  
Low Power ◽  
Design Methodology ◽  
Frequency Tuning ◽  
Supply Voltage ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Ultra Low Power ◽  
Trade Offs ◽  
Process Measurements ◽  
Lc Vco

A design methodology of CMOS LC voltage-controlled oscillator (VCO) is proposed in this paper. The relation between components and specifications of the LC-VCO is studied to easily identify its design trade-offs. This methodology has been applied to design ultra-low-power LC-VCOs for different frequency bands. An LC-VCO based on the current reuse technique has been realized with the proposed methodology in 0.13[Formula: see text][Formula: see text]m CMOS process. Measurements present an ultra-low power consumption of only 262[Formula: see text][Formula: see text]W drawn from 1[Formula: see text]V supply voltage. The measured frequency tuning range is about 10% between 2.179[Formula: see text]GHz and 2.409[Formula: see text]GHz. The post-layout simulation presents a phase noise (PN) of [Formula: see text][Formula: see text]dBc/Hz, while the measured PN is [Formula: see text][Formula: see text]dBc/Hz.

High Temperature Characterization up to 450 °C of MOSFETs and basic circuits realized in a Silicon-on-Insulator (SOI) CMOS-Technology

2012 ◽  
Vol 2012 (HITEC) ◽  
pp. 000227-000232
Author(s):  
K. Grella ◽  
S. Dreiner ◽  
A. Schmidt ◽  
W. Heiermann ◽  
H. Kappert ◽  
...  
Keyword(s):  
High Temperature ◽  
Output Voltage ◽  
Cmos Technology ◽  
Silicon On Insulator ◽  
Ring Oscillator ◽  
Maximum Temperature ◽  
Cmos Process ◽  
Ring Oscillators ◽  
Circuit Function ◽  
Soi Cmos

Standard Bulk-CMOS-technology targets use-temperatures of not more than 175 °C. Silicon-on-Insulator-technologies are commonly used up to 250 °C. In this work we evaluate the limit for electronic circuit function realized in thin film SOI-technologies for even higher temperatures. At Fraunhofer IMS a versatile 1.0 μm SOI-CMOS process based on 200 mm wafers is available. It features three layers of tungsten metalization with excellent reliability concerning electromigration, voltage independent capacitors, various resistors, and single-poly-EEPROMs. We present a study of the temperature dependence of MOSFETs and basic circuits produced in this process. The electrical characteristics of NMOSFET- and PMOSFET-transistors were studied up to 450 °C. In a second step we investigated the functionality of ring oscillators, representing digital circuits, and bandgap references as examples of simple analog components. The frequency and the current consumption of ring oscillators and the output voltage of bandgap references were also characterized up to 450 °C. We found that the ring oscillator still functions at this high temperature with a frequency of about one third of the value at room temperature. The output voltage of the bandgap reference is in the specified range up to 250 °C. The deviations above this temperature are analyzed and measures to improve the circuit are discussed. The acquired data provide an important foundation to extend the application of CMOS-technology to its real maximum temperature limits.

High Temperature Characterization up to 450°C of MOSFETs and Basic Circuits Realized in a Silicon-on-Insulator (SOI) CMOS Technology

2013 ◽  
Vol 10 (2) ◽  
pp. 67-72 ◽  
Author(s):  
K. Grella ◽  
S. Dreiner ◽  
A. Schmidt ◽  
W. Heiermann ◽  
H. Kappert ◽  
...  
Keyword(s):  
High Temperature ◽  
Band Gap ◽  
Output Voltage ◽  
Cmos Technology ◽  
Digital Circuit ◽  
Silicon On Insulator ◽  
Ring Oscillator ◽  
Maximum Temperature ◽  
Cmos Process ◽  
Soi Cmos

Standard bulk CMOS technology targets operating temperatures of not more than 175°C. Silicon-on-insulator technologies are commonly used up to 250°C. In this work, we evaluate the limit for electronic circuit function realized in thin film SOI technologies for even higher temperatures. At Fraunhofer IMS, a versatile 1.0 μm SOI-CMOS process based on 200 mm wafers is available. It features three layers of tungsten metallization with excellent reliability concerning electromigration, as well as voltage-independent capacitors, various resistors, and single-poly-EEPROMs. We present a study of the temperature dependence of MOSFETs and basic circuits produced in this process. The electrical characteristics of an NMOSFET transistor and a PMOSFET transistor are studied up to 450°C. In a second step, we investigate the functionality of a ring oscillator (representing a digital circuit) and a band gap reference as an example of a simple analog component. The frequency and the current consumption of the ring oscillator, as well as the output voltage and the current of the band gap reference, are characterized up to 450°C. We find that the ring oscillator still oscillates at this high temperature with a frequency of about one third of the value at room temperature. The output voltage of the band gap reference is in the specified range (change < 3%) up to 250°C. The deviations above this temperature are analyzed and measures to improve the circuit are discussed. The acquired data provide an important foundation to extend the application of CMOS technology to its real maximum temperature limits.

A Successive Approximation Register Analog to Digital Converter for Low Power Applications

2020 ◽  
Vol 17 (1) ◽  
pp. 451-455
Author(s):  
Yahya Mohammed Ali Al-Naamani ◽  
K. Lokesh Krishna ◽  
A. M. Guna Sekhar
Keyword(s):  
Low Power ◽  
Successive Approximation ◽  
Research Work ◽  
Implantable Devices ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Ultra Low Power ◽  
Silicon Area ◽  
Analog To Digital ◽  
Successive Approximation Register

In recent years and continuing, widespread research work is carried out on medical implantable devices placed inside the human body. The essential and vital electronic circuit in implantable devices is the Analog to Digital Converter (ADC). The essential requirements in these applications such as long battery life-time, low power consumption and less die area poses a stringent requirement in designing and fabricating an ultra-low power ADCs. Among the diverse converter architectures existing, Successive Approximation Register (SAR) type converter architecture has shown better capabilities in terms of ultra-low power operation, medium resolution, less form factor and less silicon area. In this described paper a novel power effective, better resolution SAR type ADC to be used for biomedical related applications. The proposed work consists of capacitive type Digital to Analog Converter (DAC) based on charge distribution, a CMOS comparator, and SAR logic implemented using D-flip-flops. The different blocks of SAR architecture are simulated using EDA tools in CMOS 180 nm N-well process operated at VDD = 1.5 V voltage (VDD). The circuit is measured under various input frequencies with a sampling speed of 50 MHz and it consumes 22.6 μW. The proposed ADC technology shows SNDR of 48.6 dB and occupies a circuit area of 0.11 mm2 and the measured INL and DNL is calculated to be fewer than 0.54 LSB and 0.45 LSB respectively.

scholarly journals Evaluation of Different Processor Architecture Organizations for On-Site Electronics in Harsh Environments

2020 ◽  
Author(s):  
Sven Gesper ◽  
Moritz Weißbrich ◽  
Tobias Stuckenberg ◽  
Pekka Jääskeläinen ◽  
Holger Blume ◽  
...  
Keyword(s):  
Design Space Exploration ◽  
Cmos Technology ◽  
Control Flow ◽  
Processor Architecture ◽  
Embedded Processor ◽  
Silicon Area ◽  
Trade Offs ◽  
Advanced Control ◽  
Flow Mechanisms ◽  
Technology Nodes

AbstractMicrocontrollers to be used in harsh environmental conditions, e.g., at high temperatures or radiation exposition, need to be fabricated in robust technology nodes in order to operate reliably. However, these nodes are considerably larger than cutting-edge semiconductor technologies and provide less speed, drastically reducing system performance. In order to achieve low silicon area costs, low power consumption and reasonable performance, the processor architecture organization itself is a major influential design point. Parameters like data path width, instruction execution paradigm, code density, memory requirements, advanced control flow mechanisms etc., may have large effects on the design constraints. Application characteristics, like exploitable data parallelism and required arithmetic operations, have to be considered in order to use the implemented processor resources efficiently. In this paper, a design space exploration of five different architectures with MIPS- or ARM-compatible instruction set architectures, as well as transport-triggered instruction execution is presented. Using a 0.18 $$\upmu $$ μ m SOI CMOS technology for high temperature and an exemplary case study from the fields of communication, i.e., powerline communication encoder, the influence of architectural parameters on performance and hardware efficiency is compared. For this application, a transport-triggered architecture configuration has an 8.5$$\times $$ × higher performance and 2.4$$\times $$ × higher computational energy efficiency at a 1.6$$\times $$ × larger total silicon area than an off-the-shelf ARM Cortex-M0 embedded processor, showing the considerable range of design trade-offs for different architectures.

AN OPTIMIZED LOW POWER PIPELINE ANALOG-TO-DIGITAL CONVERTER FOR HIGH-SPEED WLAN APPLICATION

2014 ◽  
Vol 23 (05) ◽  
pp. 1450059 ◽  
Author(s):  
MAO YE ◽  
BIN WU ◽  
YONGXU ZHU ◽  
YUMEI ZHOU
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
Dynamic Range ◽  
Cmos Process ◽  
Area Network ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Silicon Area ◽  
Analog To Digital

This paper presents the design and implementation of a 11-bit 160 MSPS analog-to-digital converter (ADC) for next generation super high-speed wireless local area network (WLAN) application. The ADC core consists of one front sample and hold stage and four cascades of 2.5 bit pipeline stages with opamp sharing between successive stages. To achieve low power dissipation at 1.2 V supply, a single stage symmetrical amplifier with double transimpedance gain-boosting amplifier is proposed. High speed on-chip reference buffer with replica source follower is also included for linearity performance. The ADC was fabricated in a standard 130-nm CMOS process and an occupied silicon area of 0.95 mm × 1.15 mm. Performance of 73 dB spurious-free-dynamic-range is measured at 160 MS/s with 1 Vpp input signal. The power dissipation of the analog core chip is only 50 mW from a 1.2 V supply.

scholarly journals An Adaptive STDP Learning Rule for Neuromorphic Systems

2021 ◽  
Vol 15 ◽  
Author(s):  
Ashish Gautam ◽  
Takashi Kohno
Keyword(s):  
Power Consumption ◽  
Circuit Simulation ◽  
Recognition Task ◽  
Learning Rule ◽  
Memory Storage ◽  
Cmos Process ◽  
Ultra Low Power ◽  
Silicon Area ◽  
Digital Memory ◽  
Static Power

The promise of neuromorphic computing to develop ultra-low-power intelligent devices lies in its ability to localize information processing and memory storage in synaptic circuits much like the synapses in the brain. Spiking neural networks modeled using high-resolution synapses and armed with local unsupervised learning rules like spike time-dependent plasticity (STDP) have shown promising results in tasks such as pattern detection and image classification. However, designing and implementing a conventional, multibit STDP circuit becomes complex both in terms of the circuitry and the required silicon area. In this work, we introduce a modified and hardware-friendly STDP learning (named adaptive STDP) implemented using just 4-bit synapses. We demonstrate the capability of this learning rule in a pattern recognition task, in which a neuron learns to recognize a specific spike pattern embedded within noisy inhomogeneous Poisson spikes. Our results demonstrate that the performance of the proposed learning rule (94% using just 4-bit synapses) is similar to the conventional STDP learning (96% using 64-bit floating-point precision). The models used in this study are ideal ones for a CMOS neuromorphic circuit with analog soma and synapse circuits and mixed-signal learning circuits. The learning circuit stores the synaptic weight in a 4-bit digital memory that is updated asynchronously. In circuit simulation with Taiwan Semiconductor Manufacturing Company (TSMC) 250 nm CMOS process design kit (PDK), the static power consumption of a single synapse and the energy per spike (to generate a synaptic current of amplitude 15 pA and time constant 3 ms) are less than 2 pW and 200 fJ, respectively. The static power consumption of the learning circuit is less than 135 pW, and the energy to process a pair of pre- and postsynaptic spikes corresponding to a single learning step is less than 235 pJ. A single 4-bit synapse (capable of being configured as excitatory, inhibitory, or shunting inhibitory) along with its learning circuitry and digital memory occupies around 17,250 μm2 of silicon area.

scholarly journals FAST LOW POWER FREQUENCY SYNTHESIS APPLICATIONS BY USING A DCVSL DELAY CELL

2015 ◽  
pp. 220-225
Author(s):  
N. KUMAR BABU ◽  
P. SASIBALA
Keyword(s):  
Low Power ◽  
High Speed ◽  
Schmitt Trigger ◽  
Cmos Technology ◽  
Propagation Delay ◽  
Model Parameters ◽  
Cmos Process ◽  
Ultra Low Power ◽  
Delay Cell ◽  
Parasitic Effects

In this paper, we proposed two new structures for differential cascode voltage switch logic (DCVSL) pull-up stage. In conventional DCVSL structure these lies a drawback i.e. low-to-high propagation delay is larger than high-to-low propagation delay which could be reduced by using DCVSL-R. Using resistors in DCVSL-R structure, parasitic effects are coming into picture and it occupies more area on the chip [1]. To minimize these problems we propose a new Ultra Low Power Diode (ULPD) structures in place of resistors. This provides the minimum parasitic effects and occupies less area on the chip. Second one uses Complementary Pass Transistor Logic (CPTL) structure, which provides complementary outputs. This is an alternate circuit for conventional DCVSL structure. The performances of the proposed circuits are examined using cadence and model parameters of a 180nm CMOS process. This simulation result of the two circuits is presented and is compared. These circuits are suitable for VLSI implementation. Secondly, we proposed two new CMOS Schmitt trigger circuits. These Schmitt trigger circuits are evaluated both analytically and numerically with the sources from proposed ULPD ring oscillators. The hysteresis curves of the circuits are presented. The Schmitt triggers introduced here are most suitable for high speed applications. The proposed circuits havebeen designed in TSMC-0.18μm 1.8v CMOS technology and analyzed using spectre from cadence Design systems at 50MHz and 103MHz.

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