scholarly journals T/R RF Switch with 150 ns Switching Time and over 100 dBc IMD for Wideband Mobile Applications in Thick Oxide SOI Process

Sensors ◽  
2022 ◽  
Vol 22 (2) ◽  
pp. 507
Author(s):  
Behnam S. Rikan ◽  
David Kim ◽  
Kyung-Duk Choi ◽  
Arash Hejazi ◽  
Joon-Mo Yoo ◽  
...  
Keyword(s):  
Negative Charge ◽  
Switching Time ◽  
Supply Voltage ◽  
Charge Pump ◽  
Design Rule ◽  
Absolute Maximum ◽  
Optimum Number ◽  
Rf Switch ◽  
Voltage Range ◽  
Custom Made

This paper presents a fast-switching Transmit/Receive (T/R) Single-Pole-Double-Throw (SPDT) Radio Frequency (RF) switch. Thorough analyses have been conducted to choose the optimum number of stacks, transistor sizes, gate and body voltages, to satisfy the required specifications. This switch applies six stacks of series and shunt transistors as big as 3.9 mm/160 nm and 0.75 mm/160 nm, respectively. A negative charge pump and a voltage booster generate the negative and boosted control voltages to improve the harmonics and to keep Inter-Modulation Distortion (IMD) performance of the switch over 100 dBc. A Low Drop-Out (LDO) regulator limits the boosted voltage in Absolute Maximum Rating (AMR) conditions and improves the switch performance for Process, Voltage and Temperature (PVT) variations. To reduce the size, a dense custom-made capacitor consisting of different types of capacitors has been presented where they have been placed over each other in layout considering the Design Rule Checks (DRC) and applied in negative charge pump, voltage booster and LDO. This switch has been fabricated and tested in a 90 nm Silicon-on-Insulator (SOI) process. The second and third IMD for all specified blockers remain over 100 dBc and the switching time as fast as 150 ns has been achieved. The Insertion Loss (IL) and isolation at 2.7 GHz are −0.17 dB and −33 dB, respectively. This design consumes 145 uA from supply voltage range of 1.65 V to 1.95 V and occupies 440 × 472 µm2 of die area.

scholarly journals A Negative Charge Pump Using Enhanced Pumping Clock for Low-Voltage DRAM

Electronics ◽  
2020 ◽  
Vol 9 (11) ◽  
pp. 1769 ◽  
Author(s):  
Choongkeun Lee ◽  
Taegun Yim ◽  
Hongil Yoon
Keyword(s):  
High Speed ◽  
Negative Charge ◽  
Low Voltage ◽  
Supply Voltage ◽  
Charge Pump ◽  
Clock Generator ◽  
Area Overhead ◽  
Pumping Efficiency ◽  
Charge Pump Circuit ◽  
Low Supply Voltage

As the supply voltage decreases, there is a need for a high-speed negative charge pump circuit, for example, to produce the back-bias voltage (VBB) with high pumping efficiency at a low supply voltage (VDD). Beyond the basic negative charge pump circuit with the small area overhead, advanced schemes such as hybrid pump circuit (HCP) and cross-coupled hybrid pump circuits (CHPC) were introduced to improve the pumping efficiency and pump down speed. However, they still suffer from pumping efficiency degradation, low level |VBB|, and small pumping currents at very low VDD. A novel negative charge pump using an enhanced pumping clock is proposed. The proposed cross-coupled charge pump consists of the enhanced pumping clock generator (ECG) having a pair of inverters and PMOS latch circuit to produce an enhanced control signal with a greater amplitude, thereby working efficiently especially at low supply voltages. The proposed scheme is validated with a HSPICE simulation using the TSMC 180 nm process. The proposed scheme can be operated down to VDD = 0.4 V, and |VBB|/VDD is obtained to be 86.1% at VDD = 0.5 V and Cload = 20 nF. Compared to the state-of-the-art CHPC scheme, the pumping efficiency is larger by 35% at VDD = 0.6 V and RL = 10 KΩ, and the pumping current is 2.17 times greater at VDD = 1.2 V and VBB = 0 V, making the circuit suitable for very low supply voltage applications in DRAMs.

scholarly journals Negative High Voltage DC-DC Converter Using a New Cross-Coupled Structure

2015 ◽  
Vol 10 (3) ◽  
pp. 158-165
Author(s):  
Jun Zhao ◽  
Kyung Ki Kim ◽  
Yong-Bin Kim
Keyword(s):  
High Voltage ◽  
Power Supply ◽  
Power Efficiency ◽  
Current Problem ◽  
Negative Charge ◽  
Supply Voltage ◽  
Charge Pump ◽  
Complete Analysis ◽  
Voltage Gain ◽  
Variable Voltage

In this paper, a negative high voltage DC-DC converter using a new cross-coupled charge pump structure has been proposed, which can solve the shoot-through current problem of the conventional charge pump by using a four clock phase scheme. Also, by switching the power supply to each stage based on the supply voltage, a variable voltage gain can be obtained. A complete analysis of the interaction between the power efficiency, area, and frequency have been presented. The proposed negative charge pump is designed to deliver 40μA with a widesupply range from 2.5V to 5.5V using 0.18μm high voltage LDMOS technology.

A 3.2ppm/°C curvature-compensated bandgap reference with wide supply voltage range

2012 ◽  
Vol 43 (11) ◽  
pp. 863-868 ◽  
Author(s):  
Ze-Kun Zhou ◽  
Xue-Chun Ou ◽  
Yue Shi ◽  
Pei-Sheng Zhu ◽  
Ying-Qian Ma ◽  
...  
Keyword(s):  
Supply Voltage ◽  
Bandgap Reference ◽  
Voltage Range

Design and analysis of a low noise CMOS charge pump phase locked loop circuit

2021 ◽  
pp. 2140002
Author(s):  
Yanbo Chen ◽  
Shubin Zhang
Keyword(s):  
Phase Noise ◽  
Supply Voltage ◽  
Charge Pump ◽  
Phase Locked Loop ◽  
Low Noise ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Output Frequency ◽  
Power Supply Voltage ◽  
Supply Noise

Phase Locked Loop (PLL) circuit plays an important part in electronic communication system in providing high-frequency clock, recovering the clock from data signal and so on. The performance of PLL affects the whole system. As the frequency of PLL increases, designing a PLL circuit with lower jitter and phase noise becomes a big challenge. To suppress the phase noise, the optimization of Voltage Controlled Oscillator (VCO) is very important. As the power supply voltage degrades, the VCO becomes more sensitive to supply noise. In this work, a three-stage feedforward ring VCO (FRVCO) is designed and analyzed to increase the output frequency. A novel supply-noise sensing (SNS) circuit is proposed to suppress the supply noise’s influence on output frequency. Based on these, a 1.2 V 2 GHz PLL circuit is implemented in 110 nm CMOS process. The phase noise of this CMOS charge pump (CP) PLL is 117 dBc/Hz@1 MHz from test results which proves it works successfully in suppressing phase noise.

Compact CMOS Analog Multiplier Free of Voltage Reference Generators

2020 ◽  
Vol 15 (3) ◽  
pp. 1-12
Author(s):  
Ana Isabela Araújo Cunha ◽  
Antonio José Sobrinho De Sousa ◽  
Edson Pinto Santana ◽  
Robson Nunes De Lima ◽  
Fabian Souza De Andrade ◽  
...  
Keyword(s):  
Supply Voltage ◽  
Harmonic Distortion ◽  
Current Mode ◽  
Input Voltage ◽  
Voltage Reference ◽  
Analog Multiplier ◽  
Voltage Range ◽  
Voltage Variation ◽  
Static Power ◽  
Four Quadrant

This work presents a CMOS four quadrant analog multiplier architecture for application as the synapse element in analog cellular neural networks. For this reason, the circuit has voltage-mode inputs and a current-mode output and the chief design targets are compactness and low energy consumption. A signal application method is proposed that avoids voltage reference generators, which contributes to reduce sensitivity to supply voltage variation. Performance analysis through simulation has been accomplished for a design in CMOS 130 nm technology with 163 µm2 total active area. The circuit features ±50 mV input voltage range, 86 µW static power and ‑28.4 dB maximum total harmonic distortion. A simple technique for manual calibration is also presented.

A High Temperature 4H-SiC Voltage Reference for Depletion Mode GaN-Based Circuits

2017 ◽  
Vol 2017 (HiTEN) ◽  
pp. 000118-000121
Author(s):  
ZiHao Zhang ◽  
Jebreel M. Salem ◽  
Dong Sam Ha
Keyword(s):  
High Temperature ◽  
High Temperatures ◽  
Oil And Gas ◽  
Supply Voltage ◽  
Reference Voltage ◽  
Voltage Reference ◽  
Voltage Range ◽  
Oil And Gas Exploration ◽  
Low Leakage ◽  
Temperature Applications

Abstract High temperature electronics are highly demanded for many applications such as automotive, space, and oil and gas exploration. Electronic circuits for those applications are required to operate reliably without using bulky cooling systems. Circuits based on silicon (Si) suffer from high leakage currents at high temperatures. Silicon Carbide (SiC) circuits, on the other hand, are suitable for high temperature applications due to the wide bandgap and offer high breakdown voltage and low leakage current. This paper presents a negative voltage reference for high temperature applications using commercial-off-the-shelf (COTS) 4H-SiC transistors. The proposed voltage reference adopts Widlar bandgap reference topology, and it aims to provide a negative reference voltage for Gallium Nitride (GaN) circuits operating at high temperatures. Measurement results indicate that the proposed circuit provides a negative reference voltage with a low temperature coefficient of 42 ppm/°C for temperatures ranging from 25 °C to 250 °C. The proposed circuit also operates reliably for a wide supply voltage range of −7.5 V to −15 V for the temperature range.

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