scholarly journals Design Environment for Verilog Module Analysis using Open Source Tools

2019 ◽  
Vol 9 (2S) ◽  
pp. 109-112
Keyword(s):  
Energy Efficiency ◽  
Life Cycle ◽  
Open Source ◽  
Product Life Cycle ◽  
Semiconductor Industry ◽  
Network On Chip ◽  
Design Environment ◽  
Time To Market ◽  
Distributed Routing ◽  
On Chip

Network-on-Chip provides possible solutions for the limitations and challenges by the present day architectures for the interconnections. The characteristics of NoCs include energy efficiency, reliability, scalability, reusability and distributed routing decisions. The existence of today’s semiconductor industry depends on shorter time-to-market, challenge of meeting increasing transistor density, reduced product life cycle, and operating frequencies getting higher. This paper discusses about a design environment for the analysis of Verilog NoC module. Tools such as Icarus Verilog, GTK Wave, Yosys etc. which are used for compilation, simulation and synthesis of the NoC are also discussed in this paper.

Community Customers

2011 ◽  
pp. 510-521 ◽  
Author(s):  
Jeroen Hoppenbrouwers
Keyword(s):  
Life Cycle ◽  
Open Source ◽  
Community Participation ◽  
Open Source Software ◽  
Product Life Cycle ◽  
Development Process ◽  
Sales Process ◽  
Software Product ◽  
Specific Community

This chapter discusses the role of the project/product community in the open source product life cycle. It outlines how a community-driven approach affects not only the development process, but also (and more importantly) the marketing/sales process, the deployment, the operation, and in general the resulting software product. Participation in the community is essential for any organization using the product, leading to the concept of a community customer. Specific community participation guidelines are given to organizations and individuals who deploy and use open source software, further develop it, or offer lifetime services on the product.

Sustainable Resource Management—New Legal Approaches Needed?

2012 ◽  
Vol 9 (1) ◽  
pp. 34-62 ◽  
Author(s):  
Eckard Rehbinder
Keyword(s):  
Energy Efficiency ◽  
Life Cycle ◽  
Resource Use ◽  
Product Life Cycle ◽  
Resource Scarcity ◽  
Life Cycle Thinking ◽  
Climate Protection ◽  
Eu Law ◽  
Policy Perspective ◽  
Sustainable Resource Management

Compared to climate protection and the promotion of renewable energy and energy efficiency, the saving of natural resources has been a somewhat neglected field of EU sustainability law. Based on the thesis that from an environmental policy perspective it is not resource scarcity as such but the environmental impacts associated with resource use that must be addressed, the article analyses the existing EU law and possibilities for strengthening resource efficiency and eco-efficiency in EU law. In particular, it discusses possible strategic concepts and instruments, focusing on activity-based strategies such as product life cycle thinking.

scholarly journals Industrial open source solutions for product life cycle management

2014 ◽  
Vol 1 (1) ◽  
pp. 939737 ◽  
Author(s):  
Jaime Campos ◽  
Juha Kortelainen ◽  
Erkki Jantunen ◽  
Zude Zhou
Keyword(s):  
Life Cycle ◽  
Open Source ◽  
Product Life Cycle ◽  
Life Cycle Management ◽  
Product Life ◽  
Product Life Cycle Management

scholarly journals A efficacy of different buffer size on latency of network on chip (NoC)

2019 ◽  
Vol 8 (2) ◽  
pp. 438-442
Author(s):  
Farah Wahida Binti Zulkefli ◽  
P. Ehkan ◽  
M. N. M. Warip ◽  
Ng. Yen. Phing
Keyword(s):  
Power Consumption ◽  
Semiconductor Industry ◽  
Network On Chip ◽  
Buffer Size ◽  
Large Area ◽  
Communication Architecture ◽  
Design Time ◽  
Network Topologies ◽  
On Chip ◽  
Scalable Communication

Moore's prediction has been used to set targets for research and development in semiconductor industry for years now. A burgeoning number of processing cores on a chip demand competent and scalable communication architecture such as network-on-chip (NoC). NoC technology applies networking theory and methods to on-chip communication and brings noteworthy improvements over conventional bus and crossbar interconnections. Calculated performances such as latency, throughput, and bandwidth are characterized at design time to assured the performance of NoC. However, if communication pattern or parameters set like buffer size need to be altered, there might result in large area and power consumption or increased latency. Routers with large input buffers improve the efficiency of NoC communication while routers with small buffers reduce power consumption but result in high latency. This paper intention is to validate that size of buffer exert influence to NoC performance in several different network topologies. It is concluded that the way in which routers are interrelated or arranged affect NoC’s performance (latency) where different buffer sizes were adapted. That is why buffering requirements for different routers may vary based on their location in the network and the tasks assigned to them.

scholarly journals A Middleware Approach to Achieving Fault Tolerance of Kahn Process Networks on Networks on Chips

2011 ◽  
Vol 2011 ◽  
pp. 1-15 ◽  
Author(s):  
Onur Derin ◽  
Erkan Diken ◽  
Leandro Fiorin
Keyword(s):  
Fault Tolerance ◽  
Open Source ◽  
Execution Time ◽  
Initial Step ◽  
Network On Chip ◽  
Distributed Model ◽  
Total Execution Time ◽  
Process Networks ◽  
Kahn Process ◽  
On Chip

Kahn process networks (KPNs) is a distributed model of computation used for describing systems where streams of data are transformed by processes executing in sequence or parallel. Autonomous processes communicate through unbounded FIFO channels in absence of a global scheduler. In this work, we propose a task-aware middleware concept that allows adaptivity in KPN implemented over a Network on Chip (NoC). We also list our ideas on the development of a simulation platform as an initial step towards creating fault tolerance strategies for KPNs applications running on NoCs. In doing that, we extend our SACRE (Self-Adaptive Component Run Time Environment) framework by integrating it with an open source NoC simulator, Noxim. We evaluate the overhead that the middleware brings to the the total execution time and to the total amount of data transferred in the NoC. With this work, we also provide a methodology that can help in identifying the requirements and implementing fault tolerance and adaptivity support on real platforms.

scholarly journals Hybrid Network-on-Chip: An Application-Aware Framework for Big Data

Complexity ◽  
2018 ◽  
Vol 2018 ◽  
pp. 1-11
Author(s):  
Juan Fang ◽  
Sitong Liu ◽  
Shijian Liu ◽  
Yanjin Cheng ◽  
Lu Yu
Keyword(s):  
Energy Efficiency ◽  
Big Data ◽  
Power Consumption ◽  
High Performance ◽  
Network On Chip ◽  
Hybrid Network ◽  
Big Data Applications ◽  
Application Aware ◽  
On Chip ◽  
Many Core

Burst growing IoT and cloud computing demand exascale computing systems with high performance and low power consumption to process massive amounts of data. Modern system platforms based on fundamental requirements encounter a performance gap in chasing exponential growth in data speed and amount. To narrow the gap, a heterogamous design gives us a hint. A network-on-chip (NoC) introduces a packet-switched fabric for on-chip communication and becomes the de facto many-core interconnection mechanism; it refers to a vital shared resource for multifarious applications which will notably affect system energy efficiency. Among all the challenges in NoC, unaware application behaviors bring about considerable congestion, which wastes huge amounts of bandwidth and power consumption on the chip. In this paper, we propose a hybrid NoC framework, combining buffered and bufferless NoCs, to make the NoC framework aware of applications’ performance demands. An optimized congestion control scheme is also devised to satisfy the requirement in energy efficiency and the fairness of big data applications. We use a trace-driven simulator to model big data applications. Compared with the classical buffered NoC, the proposed hybrid NoC is able to significantly improve the performance of mixed applications by 17% on average and 24% at the most, decrease the power consumption by 38%, and improve the fairness by 13.3%.

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