scholarly journals Design of Improved 8:1 Multiplexer using Quantum-dot Cellular Automata Technology

2020 ◽  
Vol 9 (1) ◽  
pp. 2659-2662
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Cell Count ◽  
Power Dissipation ◽  
Quantum Physics ◽  
Logic Circuits ◽  
Digital Logic ◽  
Quantum Dot Cellular Automata

A much-required breakthrough in the field of VLSI took place with the birth of Quantum-dot cellular automata (QCA) technology, an impressive amalgamation of Quantum Physics and Nanotechnology and acted as a possible replacement to the age-old semiconductor transistor-based designs (CMOS) with Boolean paradigm. In this paper, we aim at implementing this technology to build a robust 8:1 multiplexer that can help in building and developing many more digital logic circuits, from an already proposed 2:1 multiplexer. It has excellent efficiency with respect to least cell count, latency, space and power dissipation.

scholarly journals A Customizable Quantum-Dot Cellular Automata Building Block for the Synthesis of Classical and Reversible Circuits

2015 ◽  
Vol 2015 ◽  
pp. 1-9 ◽  
Author(s):  
Ahmed Moustafa ◽  
Ahmed Younes ◽  
Yasser F. Hassan
Keyword(s):  
Quantum Dots ◽  
Cellular Automata ◽  
Quantum Dot ◽  
Cell Count ◽  
Building Block ◽  
Digital Logic ◽  
Basic Building Block ◽  
Quantum Dot Cellular Automata ◽  
Binary Operations ◽  
Toffoli Gates

Quantum-dot cellular automata (QCA) are nanoscale digital logic constructs that use electrons in arrays of quantum dots to carry out binary operations. In this paper, a basic building block for QCA will be proposed. The proposed basic building block can be customized to implement classical gates, such as XOR and XNOR gates, and reversible gates, such as CNOT and Toffoli gates, with less cell count and/or better latency than other proposed designs.

Towards the Design of Cost-efficient Generic Register Using Quantum-dot Cellular Automata

2020 ◽  
Vol 10 (4) ◽  
pp. 534-547
Author(s):  
Chiradeep Mukherjee ◽  
Saradindu Panda ◽  
Asish K. Mukhopadhyay ◽  
Bansibadan Maji
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Power Dissipation ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Digital Data ◽  
Design Parameters ◽  
Flip Flop ◽  
Quantum Dot Cellular Automata ◽  
Cost Efficient

Background: The advancement of VLSI in the application of emerging nanotechnology explores quantum-dot cellular automata (QCA) which has got wide acceptance owing to its ultra-high operating speed, extremely low power dissipation with a considerable reduction in feature size. The QCA architectures are emerging as a potential alternative to the conventional complementary metal oxide semiconductor (CMOS) technology. Experimental: Since the register unit has a crucial role in digital data transfer between the electronic devices, such study leading to the design of cost-efficient and highly reliable QCA register is expected to be a prudent area of research. A thorough survey on the existing literature shows that the generic models of Serial-in Serial Out (SISO), Serial-in-Parallel-Out (SIPO), Parallel-In- Serial-Out (PISO) and Parallel-in-Parallel-Out (PIPO) registers are inadequate in terms of design parameters like effective area, delay, O-Cost, Costα, etc. Results: This work introduces a layered T gate for the design of the D flip flop (LTD unit), which can be broadly used in SISO, SIPO, PISO, and PIPO register designs. For detection and reporting of high susceptible errors and defects at the nanoscale, the reliability and defect tolerant analysis of LTD unit are also carried out in this work. The QCA design metrics for the general register layouts using LTD unit is modeled. Conclusion: Moreover, the cost metrics for the proposed LTD layouts are thoroughly studied to check the functional complexity, fabrication difficulty and irreversible power dissipation of QCA register layouts.

Toward Efficient Design of Flip-flops in Quantum-Dot Cellular Automata with Power Dissipation Analysis

2018 ◽  
Vol 57 (11) ◽  
pp. 3419-3428 ◽  
Author(s):  
Ali Newaz Bahar ◽  
Radhouane Laajimi ◽  
Md. Abdullah-Al-Shafi ◽  
Kawsar Ahmed
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Power Dissipation ◽  
Efficient Design ◽  
Quantum Dot Cellular Automata

Estimation of Power Dissipation in Ternary Quantum Dot Cellular Automata Cell

2017 ◽  
Vol 13 (2) ◽  
pp. 231-239
Author(s):  
Pritam Bhattacharjee ◽  
Kunal Das ◽  
Arijit Dey ◽  
Debashis De ◽  
Swarnendu Kumar Chakraborty
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Power Dissipation ◽  
Quantum Dot Cellular Automata

scholarly journals An Efficient Design of DCT Approximation Based on Quantum Dot Cellular Automata (QCA) Technology

2019 ◽  
Vol 2019 ◽  
pp. 1-11 ◽  
Author(s):  
Ismail Gassoumi ◽  
Lamjed Touil ◽  
Bouraoui Ouni ◽  
Abdellatif Mtibaa
Keyword(s):  
Image Processing ◽  
Cellular Automata ◽  
Quantum Dot ◽  
Low Power ◽  
Video Compression ◽  
Video Processing ◽  
Power Dissipation ◽  
Functional Verification ◽  
Efficient Design ◽  
Quantum Dot Cellular Automata

Optimization for power is one of the most important design objectives in modern digital image processing applications. The DCT is considered to be one of the most essential techniques in image and video compression systems, and consequently a number of extensive works had been carried out by researchers on the power optimization. On the other hand, quantum-dot cellular automata (QCA) can present a novel opportunity for the design of highly parallel architectures and algorithms for improving the performance of image and video processing systems. Furthermore, it has considerable advantages in comparison with CMOS technology, such as extremely low power dissipation, high operating frequency, and a small size. Therefore, in this study, the authors propose a multiplier-less DCT architecture in QCA technology. The proposed design provides high circuit performance, very low power consumption, and very low dimension outperform to the existing conventional structures. The QCADesigner tool has been utilized for QCA circuit design and functional verification of all designs in this work. QCAPro, a very widespread power estimator tool, is applied to estimate the power dissipation of the proposed circuit. The suggested design has 53% improvement in terms of power over the conventional solution. The outcome of this work can clearly open up a new window of opportunity for low power image processing systems.

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