scholarly journals Dynamic Offset Compensated Operational Amplifiers

2021 ◽  
Author(s):  
Ara Abdulsatar Assim Assim ◽  
Evgenii Balashov
Keyword(s):  
Dynamic Range ◽  
Flicker Noise ◽  
Input Voltage ◽  
High Gain ◽  
Operational Amplifiers ◽  
Analog To Digital ◽  
Offset Cancellation ◽  
Offset Voltage ◽  
Low Offset ◽  
The Given

The given work is devoted to designing and implementing different dynamic offset cancellation techniques for 50 nm technology CMOS operational amplifiers. The goal is to minimize or get rid of the effects of the offset voltage. Offset voltage exists in all differential amplifiers due to the fact that no pair of transistors can be fabricated with the same size, there is always a slight difference in their dimensions (length or width), this gives rise to an undesirable effect called offset, the value of offset voltage for cheap commercial amplifiers are in the range of 1 to 10 mV, de-spite the fact that this isn’t a significant value, due to the high gain of such amplifiers, this voltage is amplified by tens or hundreds of times, this results in clipping of the output signal and this further limits the amplifier’s maximum allowable input voltage within the given dynamic range, hence its of great importance to take this small voltage into consideration, low-offset amplifiers find applications in mixers, analog to digital converters, instrumentation devices, etc. In this thesis, by using two different techniques for removing offset voltage (chopping and auto-zeroing), five low offset operational amplifiers were designed. The implemented methods reduced the flicker noise by more than 457 times (from 9.4 nV/√Hz to 20 pV/√Hz) at 1 Hz. All the simulations were done using Cadence Virtuoso.

scholarly journals Dynamic Offset Compensated Operational Amplifiers

2021 ◽  
Author(s):  
Ara Abdulsatar Assim Assim ◽  
Evgenii Balashov
Keyword(s):  
Dynamic Range ◽  
Flicker Noise ◽  
Input Voltage ◽  
High Gain ◽  
Operational Amplifiers ◽  
Analog To Digital ◽  
Offset Cancellation ◽  
Offset Voltage ◽  
Low Offset ◽  
The Given

The given work is devoted to designing and implementing different dynamic offset cancellation techniques for 50 nm technology CMOS operational amplifiers. The goal is to minimize or get rid of the effects of the offset voltage. Offset voltage exists in all differential amplifiers due to the fact that no pair of transistors can be fabricated with the same size, there is always a slight difference in their dimensions (length or width), this gives rise to an undesirable effect called offset, the value of offset voltage for cheap commercial amplifiers are in the range of 1 to 10 mV, de-spite the fact that this isn’t a significant value, due to the high gain of such amplifiers, this voltage is amplified by tens or hundreds of times, this results in clipping of the output signal and this further limits the amplifier’s maximum allowable input voltage within the given dynamic range, hence its of great importance to take this small voltage into consideration, low-offset amplifiers find applications in mixers, analog to digital converters, instrumentation devices, etc. In this thesis, by using two different techniques for removing offset voltage (chopping and auto-zeroing), five low offset operational amplifiers were designed. The implemented methods reduced the flicker noise by more than 457 times (from 9.4 nV/√Hz to 20 pV/√Hz) at 1 Hz. All the simulations were done using Cadence Virtuoso.

A LOW OFFSET HIGH SPEED COMPARATOR FOR PIPELINE ADC

2013 ◽  
Vol 22 (04) ◽  
pp. 1350018 ◽  
Author(s):  
ZHANGMING ZHU ◽  
HONGBING WU ◽  
GUANGWEN YU ◽  
YANHONG LI ◽  
LIANXI LIU ◽  
...  
Keyword(s):  
Monte Carlo Simulation ◽  
Power Dissipation ◽  
High Speed ◽  
Cmos Process ◽  
Pipeline Adc ◽  
Analog To Digital ◽  
Offset Cancellation ◽  
Reduction Techniques ◽  
Offset Voltage ◽  
Low Offset

A low offset and high speed preamplifier latch comparator is proposed for high-speed pipeline analog-to-digital converters (ADCs). In order to realize low offset, both offset cancellation techniques and kickback noise reduction techniques are adopted. Based on TSMC 0.18 μm 3.3 V CMOS process, Monte Carlo simulation shows that the comparator has a low offset voltage 1.1806 mV at 1 sigma at 125 MHz, with a power dissipation of 413.48 μW.

An Improved Low-Offset and Low-Power Design of Comparator for Flash ADC

2014 ◽  
Vol 598 ◽  
pp. 365-370
Author(s):  
Shuo Zhang ◽  
Zong Min Wang ◽  
Liang Zhou
Keyword(s):  
Low Power ◽  
Low Power Design ◽  
Cmos Process ◽  
Total Current ◽  
Flash Adc ◽  
Analog To Digital ◽  
Offset Cancellation ◽  
Offset Voltage ◽  
Current Consumption ◽  
Low Offset

This paper presents an offset-cancellation and low power cascaded comparator with new technique for flash Analog-to-Digital Converters. The improved structure cancels both input and output offset voltage by the feedback from outputs to common inputs. The total current consumption is reduced sharply for a clock circle with 1:2 dutyratio. The improved comparator is implemented in 0.35μm CMOS process. The Spectre simulation results show that the offset voltage of the improved structure is 3.14996mV with σ = 2.0347mV,and total current consumption is 17.59μA, while the offset voltage and total current consumption of the primary one is -5.649mV with σ = 14.254mV and 57.18μA respectively.

High Performance Analysis of CDS Delta-Sigma ADC in 45-Nanometer Regime

2014 ◽  
Vol 13 (01) ◽  
pp. 1450003
Author(s):  
Bhanupriya Bhargava ◽  
Pradeep Kumar Sharma ◽  
Shyam Akashe
Keyword(s):  
High Speed ◽  
Flicker Noise ◽  
Supply Voltage ◽  
Frequency Noise ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Analog To Digital ◽  
Op Amp ◽  
Offset Voltage ◽  
Delta Sigma

In this paper, a correlated double sampling (CDS) technique is proposed in the design of a delta sigma analog-to-digital converter (ADC). These CDS techniques are very effective for the compensation of the nonidealities in switched-capacitor (SC) circuits, such as charge injection, clock feed-through, operational amplifier (op-amp) input-referred offset and finite op-amp gain. An improved compensation scheme is proposed to attain continuous compensation of clock feed-through and offset in SC integrators. Both high-speed and low-power operation is achieved without compromising the accuracy requirement. Also this CDS delta sigma ADC is the most promising circuit for analog to digital converter because this circuit reduces noise due to drift and low frequency noise such as flicker noise and offset voltage and also boosts the gain performance of the amplifier. Further, the simulation results of this circuit are verified on using a "cadence virtuoso tool" using spectre at 45 nm technology with supply voltage 0.7 V.

Ultralow Noise Low Offset Chopper Amplifier for Induction Coil Sensor to Detect Geomagnetic Field of 1 mHz to 1 kHz

2020 ◽  
Vol 25 (4) ◽  
pp. 497-511
Author(s):  
Jiawei Li ◽  
Zhenzhu Xi ◽  
Xingpeng Chen ◽  
He Wang ◽  
Xia Long ◽  
...  
Keyword(s):  
Geomagnetic Field ◽  
Low Frequency ◽  
Input Voltage ◽  
Induction Coil ◽  
Corner Frequency ◽  
Offset Voltage ◽  
Key Factor ◽  
Time Drift ◽  
Chopper Amplifier ◽  
Low Offset

An induction coil sensor (ICS) is important for measuring low-frequency (DC-1kHz) geomagnetic field. The accuracy of the preamplifier is one key factor determining the performance of the sensor. But the preamplifier is susceptible to 1/ f noise, offset voltage and drift. In order to eliminate these influences, a preamplifier circuit with three amplifier stages based on chopper technology has been designed, and its performance has been tested. The results show that: 1) The 1/ f noise corner frequency is 3 mHz, the equivalent input voltage noise (EIVN) level of the circuit is [Formula: see text] and [Formula: see text]; 2) The equivalent input current noise (EICN) level of the circuit is [Formula: see text]; 3) The offset voltage is about 600 nV, and the time drift performance is excellent. In conclusion, the preamplifier circuit has characteristics of ultralow noise, low offset voltage and low time drift. It can effectively amplify low-frequency weak geomagnetic signals from 1 mHz to 1 kHz and provides excellent performance for low-frequency ICS.

scholarly journals MOCVD-Grown InGa/GaAs Emitter Delta Doping Heterojunction Bipolar Transistors

2002 ◽  
Vol 25 (3) ◽  
pp. 239-243
Author(s):  
K. F. Yarn
Keyword(s):  
Heterojunction Bipolar Transistors ◽  
High Gain ◽  
Bipolar Transistors ◽  
Heterojunction Bipolar Transistor ◽  
Current Gain ◽  
Offset Voltage ◽  
Delta Doping ◽  
Spacer Layer ◽  
Potential Spike ◽  
Low Offset

The influence of delta doping sheet at base-emitter (BE) junction for an InGaP/GaAs heterojunction bipolar transistor (HBT) with a 75Å undoped spacer layer is investigated. A common emitter current gain of 235, an offset voltage as small as 50mV and an Ic ideal factor of 1.01 are obtained, respectively. The use of delta doping sheet at BE junction results in a high gain and low offset voltage HBT. The improvement of current gain and offset voltage may be attributed to the reduction of BE potential spike by introducing a delta doping layer even without the BE junction passivation.

scholarly journals A High-Speed and Low-Offset Dynamic Latch Comparator

2014 ◽  
Vol 2014 ◽  
pp. 1-8 ◽  
Author(s):  
Labonnah Farzana Rahman ◽  
Mamun Bin Ibne Reaz ◽  
Chia Chieu Yin ◽  
Mohammad Marufuzzaman ◽  
Mohammad Anisur Rahman
Keyword(s):  
Monte Carlo Simulation ◽  
Monte Carlo ◽  
Power Dissipation ◽  
High Speed ◽  
Cmos Process ◽  
Clock Frequency ◽  
Analog To Digital ◽  
Offset Voltage ◽  
Simulation Results ◽  
Low Offset

Circuit intricacy, speed, low-offset voltage, and resolution are essential factors for high-speed applications like analog-to-digital converters (ADCs). The comparator circuit with preamplifier increases the power dissipation, as it requires higher amount of currents than the latch circuitry. In this research, a novel topology of dynamic latch comparator is illustrated, which is able to provide high speed, low offset, and high resolution. Moreover, the circuit is able to reduce the power dissipation as the topology is based on latch circuitry. The cross-coupled circuit mechanism with the regenerative latch is employed for enhancing the dynamic latch comparator performance. In addition, input-tracking phase is used to reduce the offset voltage. The Monte-Carlo simulation results for the designed comparator in 0.18 μm CMOS process show that the equivalent input-referred offset voltage is 720 μV with 3.44 mV standard deviation. The simulated result shows that the designed comparator has 8-bit resolution and dissipates 158.5 μW of power under 1.8 V supply while operating with a clock frequency of 50 MHz. In addition, the proposed dynamic latch comparator has a layout size of148.80 μm×59.70 μm.

scholarly journals A 5 Bit 600MS/S Asynchronous Digital Slope ADC with Modified Strong Arm Comparator

2019 ◽  
Vol 9 (1S5) ◽  
pp. 41-44
Keyword(s):  
Power Dissipation ◽  
High Speed ◽  
Average Power ◽  
Cmos Technology ◽  
Analog To Digital ◽  
Delay Cell ◽  
Offset Voltage ◽  
Static Power ◽  
Cell Sample ◽  
Low Offset

Strong arm comparator has some characteristics like it devours zero static power and yields rail to rail swing. It acquires a positive feedback allowed by two cross coupled pairs of comparators and results a low offset voltage in input differential stage. We modified a strong arm Comparator for high speed without relying on complex calibration Schemes. a 5- bit 600MS/s asynchronous digital slope analog to digital converter (ADS-ADC) with modified strong arm comparator designed in cadence virtuoso at 180nm CMOS technology. The design of SR-Latch using Pseudo NMOS NOR Gate optimizes the speed. Thus delay reduced in select signal generation block. Power dissipation is minimized with lesser transistor count in Strong arm comparator and SR-Latch with maximum sampling speed. The speed of the converter can be improved by resolution. The proposed circuit is 5-bit ADC containing a delay cell, Sample and hold, continuous time comparator, strong arm comparator, Pseudo NMOS SR-Latch and Multiplexer. This 5- bit ADC operates voltage at 1.8 volts and consumes an average power.

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