A CMOS Input Buffer for High-Resolution A/D Converters with High Sampling Rates

2014 ◽  
Vol 678 ◽  
pp. 497-500
Author(s):  
Xing Fa Huang ◽  
Rong Bin Hu ◽  
Liang Li
Keyword(s):  
High Resolution ◽  
Input Signal ◽  
High Speed ◽  
Process Technology ◽  
Input Buffer ◽  
Design And Implementation ◽  
High Linearity ◽  
High Sampling

With respect to the application of high-speed, high-resolution A/D converter, the design and implementation of a CMOS input buffer is introduced. The buffer features high-speed and high-linearity. Its performances have been verified in a 14-bit 250MSPS pipelined A/D converter which is developed in 0.18um CMOS-based process technology. The simulation shows that the SFDR of the buffer is up to 104dB at an input clock of 250MHz with an input signal of 25MHz.

Electrical Probing and Surface Imaging of Deep Sub-Micron Integrated Circuits

1999 ◽  
Author(s):  
Kenneth Krieg ◽  
Richard Qi ◽  
Douglas Thomson ◽  
Greg Bridges
Keyword(s):  
High Resolution ◽  
Integrated Circuits ◽  
Real Time ◽  
High Speed ◽  
Time Signal ◽  
Surface Imaging ◽  
Atomic Force ◽  
Submicron Structures ◽  
High Resolution Images ◽  
Capacitive Loading

Abstract A contact probing system for surface imaging and real-time signal measurement of deep sub-micron integrated circuits is discussed. The probe fits on a standard probe-station and utilizes a conductive atomic force microscope tip to rapidly measure the surface topography and acquire real-time highfrequency signals from features as small as 0.18 micron. The micromachined probe structure minimizes parasitic coupling and the probe achieves a bandwidth greater than 3 GHz, with a capacitive loading of less than 120 fF. High-resolution images of submicron structures and waveforms acquired from high-speed devices are presented.

scholarly journals A Low-Power 12-Bit 20 MS/s Asynchronously Controlled SAR ADC for WAVE ITS Sensor Based Applications

Sensors ◽  
2021 ◽  
Vol 21 (7) ◽  
pp. 2260
Author(s):  
Khuram Shehzad ◽  
Deeksha Verma ◽  
Danial Khan ◽  
Qurat Ul Ain ◽  
Muhammad Basim ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Intelligent Transportation System ◽  
Cmos Process ◽  
Process Technology ◽  
Back Issue ◽  
Digital To Analog Converter ◽  
Analog To Digital ◽  
Switching Method

A low power 12-bit, 20 MS/s asynchronously controlled successive approximation register (SAR) analog-to-digital converter (ADC) to be used in wireless access for vehicular environment (WAVE) intelligent transportation system (ITS) sensor based application is presented in this paper. To optimize the architecture with respect to power consumption and performance, several techniques are proposed. A switching method which employs the common mode charge recovery (CMCR) switching process is presented for capacitive digital-to-analog converter (CDAC) part to lower the switching energy. The switching technique proposed in our work consumes 56.3% less energy in comparison with conventional CMCR switching method. For high speed operation with low power consumption and to overcome the kick back issue in the comparator part, a mutated dynamic-latch comparator with cascode is implemented. In addition, to optimize the flexibility relating to the performance of logic part, an asynchronous topology is employed. The structure is fabricated in 65 nm CMOS process technology with an active area of 0.14 mm2. With a sampling frequency of 20 MS/s, the proposed architecture attains signal-to-noise distortion ratio (SNDR) of 65.44 dB at Nyquist frequency while consuming only 472.2 µW with 1 V power supply.

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