An Improved Architecture for Multi-Core Prefetching

The “Memory Wall” problem has become a bottleneck for the performance of processor, and on-chip multiprocessor(CMP) aggravates the memory access latency. So many hardware prefetching techniques have been brought to solve this challenge, i.e. Future Execution. This paper introduces runahead execution(another hardware prefetching technique firstly used on single-core processor) and Future Execution, then it brings up some improvement for Future Execution and gives the result and analysis of data tested by SPEC2000 benchmark.