ABSTRACTThe metal nanocrystal (NC) based carbon nanotube (CNT) memory device has been probed with tunneling rate measurements. Firstly, tunneling behavior at two temperatures (300K and 10K) is reported here to demonstrate the distinct charge tunneling behavior for traps versus NCs and understand their relative contributions to program operations. Low temperature measurements show clear differentiation for two regimes of quantum transport. The FN tunneling regime exhibits strong bias dependence and dominates at high electric fields producing larger tunneling rates than the direct tunneling regime. In comparison to traps, the metal NCs repel potential contours and hence produce higher electric fields that enhance tunneling. The FN tunneling diminishes when the charging of the nanocrystal or traps decreases (relaxes) the electric field in the tunnel dielectric (TD) enough for the low field direct tunneling to dominate. The direct tunneling occurs at low fields, and is less sensitive to electric fields. The NCs demonstrate faster tunneling which can be ascribed to their large tunneling cross-section compared to traps. This is despite the relative proximity of traps to the channel in our structure. Secondly, the tunneling rates for two different TDs of similar EOT (under linear approximation) have been characterized and compared. They are a homogenous evaporated SiO2 and layered dielectric consisting of an evaporated SiO2 and ALD Al2O3 stack. While the evaporated SiO2 based TD demonstrates the distinct NC versus trap tunnel rate performance, the layered TD demonstrates stronger resistance to tunneling to the NCs. This result is consistent with the low tunneling rates demonstrated in Al2O3 elsewhere. Finally, the program performance of the NC-CNT memory device is evaluated as 0.5 V threshold voltage (VT) shift for a charging pulse of 9V and 100 μs. Combining with previous results, this indicates that NC-CNT memory is a promising candidate for low voltage, fast, multi-level cell (MLC) operation with sub-lithographic (self-assembled) features for sub 30 nm FLASH memory node. From the device physics perspective, these measurements may serve as the calibration and validation for advanced tunneling calculations and device modeling for promising nanoscale charge-based non-volatile memories.
