Performance Improvement of Trench-Gate SiC MOSFETs by Localized High-Concentration N-Type Ion Implantation

2020 ◽  
Vol 1004 ◽  
pp. 770-775
Author(s):  
Rina Tanaka ◽  
Katsutoshi Sugawara ◽  
Yutaka Fukui ◽  
Hideyuki Hatta ◽  
Hidenori Koketsu ◽  
...  
Keyword(s):  
Performance Improvement ◽  
Short Circuit ◽  
Effective Means ◽  
Gate Oxide ◽  
Device Performance ◽  
High Concentration ◽  
Safe Operation ◽  
Major Drawback ◽  
Oxide Reliability ◽  
Conventional Device

Gate oxide reliability of a trench-gate SiC MOSFET can be improved by incorporating a gate protection structure, but the resulting parasitic JFET resistance is one major drawback. For reduction of on-resistance, a new method of localized high-concentration n-type doping in JFET regions (JD) is developed. Utilizing process and device simulation by TCAD, the optimal condition of JD that enables maximum device performance is derived. By fabricating a device with the optimal JD structure, the on-resistance is successfully reduced by 25% compared to a conventional device without JD, while maintaining the withstand voltage and the gate oxide electric field at the same level. As a result, a device exhibiting a specific on-resistance of 1.84 mΩcm2 and a breakdown voltage of 1560 V is obtained. The optimal JD structure maintains the short-circuit safe operation area comparable to that for the structure without JD. Thus, by reducing the JFET resistance while minimizing effects on other characteristics, localized JD is shown to be an effective means of realizing a reliable, low-resistance SiC power device.

Tunneling Effects in NH3 Annealed 4H-SiC Trench MOSFETs

2020 ◽  
Vol 1004 ◽  
pp. 652-658
Author(s):  
Judith Berens ◽  
Gregor Pobegen ◽  
Tibor Grasser
Keyword(s):  
Effective Activation Energy ◽  
Charge Trapping ◽  
Gate Oxide ◽  
Device Performance ◽  
Trap Level ◽  
Effective Activation ◽  
Oxide Reliability ◽  
Trap Assisted Tunneling ◽  
Assisted Tunneling ◽  
Mos Structures

The interface between the gate oxide and silicon carbide (SiC) has a strong influence on the performance and reliability of SiC MOSFETs and thus, requires special attention. In order to reduce charge trapping at the interface, post oxidation anneals (POAs) are conventionally applied. However, these anneals do not only influence the device performance, such as mobility and on-resistance, but also the gate oxide reliability. We study the oxide tunneling mechanisms of NH3 annealed 4H-SiC trench MOSFET test structures and compare them to devices which received a NO POA. We show that 3 different mechanisms, namely trap assisted tunneling (TAT), Fowler-Nordheim (FN) tunneling and charge trapping are found for NH3 annealed MOS structures whereas only FN-tunneling is observed in NO annealed devices.The tunneling barrier suggest a trap level with an effective activation energy of 382 meV to enable TAT.

Reliability and Ruggedness of 1200V SiC Planar Gate MOSFETs Fabricated in a High Volume CMOS Foundry

2018 ◽  
Vol 924 ◽  
pp. 697-702 ◽  
Author(s):  
Sauvik Chowdhury ◽  
Levi Gant ◽  
Blake Powell ◽  
Kasturirangan Rangaswamy ◽  
Kevin Matocha
Keyword(s):  
Room Temperature ◽  
Stress Testing ◽  
Short Circuit ◽  
Gate Oxide ◽  
High Volume ◽  
Inductive Load ◽  
Switching Losses ◽  
Oxide Reliability ◽  
Silicon Cmos

This paper presents the performance, reliability and ruggedness characterization of 1200V, 80mΩ rated SiC planar gate MOSFETs, fabricated in a high volume, 150mm silicon CMOS foundry. The devices showed a specific on-resistance of 5.1 mΩ.cm2 at room temperature, increasing to 7.5 mΩ.cm2 at 175 °C. Total switching losses were less than 300μJ (VDD = 800V, ID = 20A). The devices showed excellent gate oxide reliability with VTH shifts under 0.2V for extended HTGB stress testing at 175 °C for up to 5500 hours (VGS = 25V) and 2500 hours (VGS = -10V). Ruggedness performance such as unclamped inductive load switching and short circuit capability are also discussed.

Impact of boron penetration on gate oxide reliability and device performance in a dual-gate oxide process

2000 ◽  
Author(s):  
Yunqiang Zhang ◽  
Chock H. Gan ◽  
Xi Li ◽  
James Lee ◽  
David Vigar ◽  
...  
Keyword(s):  
Gate Oxide ◽  
Device Performance ◽  
Oxide Reliability ◽  
Dual Gate ◽  
Boron Penetration

4H-SiC Trench MOSFET with Bottom Oxide Protection

2014 ◽  
Vol 778-780 ◽  
pp. 919-922 ◽  
Author(s):  
Yasuhiro Kagawa ◽  
Nobuo Fujiwara ◽  
Katsutoshi Sugawara ◽  
Rina Tanaka ◽  
Yutaka Fukui ◽  
...  
Keyword(s):  
Electric Field ◽  
Dynamic Characteristics ◽  
Effective Means ◽  
Gate Oxide ◽  
Switching Loss ◽  
Type Region ◽  
Oxide Reliability ◽  
Effective Reduction ◽  
P Type

Ensuring gate oxide reliability and low switching loss is required for a trench gate SiC-MOSFET. We developed a trench gate SiC-MOSFET with a p-type region, named Bottom P-Well (BPW), formed at the bottom of the trench gate for bottom oxide protection. We can see an effective reduction in the maximum bottom oxide electric field (Eox) and a significant improvement in dynamic characteristics with a grounded BPW, whose dV/dt is 76 % larger than that with a floating BPW due to reduction in gate-drain capacitance (Cgd). The grounded BPW is found to be an effective means of both suppressing Eox and reducing switching loss.

Gate Oxide Reliability Issues of SiC MOSFETs Under Short-Circuit Operation

2015 ◽  
Vol 30 (5) ◽  
pp. 2445-2455 ◽  
Author(s):  
Thanh-That Nguyen ◽  
Ashraf Ahmed ◽  
T. V. Thang ◽  
Joung-Hu Park
Keyword(s):  
Short Circuit ◽  
Gate Oxide ◽  
Oxide Reliability

A Novel High-Stress Pre-Metal Dielectric Film to Improve Device Performance for sub-65nm CMOS Manufacturing

2006 ◽  
Vol 913 ◽  
Author(s):  
Young Way Teh ◽  
John Sudijono ◽  
Alok Jain ◽  
Shankar Venkataraman ◽  
Sunder Thirupapuliyur ◽  
...  
Keyword(s):  
Performance Improvement ◽  
Dielectric Film ◽  
High Stress ◽  
Significant Degree ◽  
Strain Effect ◽  
Device Performance ◽  
Hot Carrier ◽  
Tcad Simulation ◽  
Improve Device ◽  
Deposition Techniques

AbstractThis work focuses on the development and physical characteristics of a novel dielectric film for a pre-metal dielectric (PMD) application which induces a significant degree of tensile stress in the channel of a sub-65nm node CMOS structure. The film can be deposited at low temperatures to meet the requirements of NiSi integration while maintaining void-free gap fill and superior film quality such as moisture content and uniformity. A manufacturable and highly reliable oxide film has been demonstrated through both TCAD simulation and real device data, showing ~6% NMOS Ion-Ioff improvement; no Ion-Ioff improvement or degradation on PMOS. A new concept has been proposed to explain the PMD strain effect on device performance improvement. Improvement in Hot Carrier immunity is observed compared to similar existing technologies using high density plasma (HDP) deposition techniques.

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