scholarly journals Performance Optimization of 1-bit Full Adder Cell based on CNTFET Transistor

2019 ◽  
Vol 9 (6) ◽  
pp. 4933-4936
Author(s):  
H. Ghabri ◽  
D. Ben Issa ◽  
H. Samet

The full adder is a key component for many digital circuits like microprocessors or digital signal processors. Its main utilization is to perform logical and arithmetic operations. This has empowered the designers to continuously optimize this circuit and ameliorate its characteristics like robustness, compactness, efficiency, and scalability. Carbon Nanotube Field Effect Transistor (CNFET) stands out as a substitute for CMOS technology for designing circuits in the present-day technology. The objective of this paper is to present an optimized 1-bit full adder design based on CNTFET transistors inspired by new CMOS full adder design [1] with enhanced performance parameters. For a power supply of 0.9V, the count of transistors is decreased to 10 and the power is almost split in two compared to the best existing CNTFET based adder. This design offers significant improvement when compared to existing designs such as C-CMOS, TFA, TGA, HPSC, 18T-FA adder, etc. Comparative data analysis shows that there is 37%, 50%, and 49% amelioration in terms of area, delay, and power delay product respectively compared to both CNTFET and CMOS based adders in existing designs. The circuit was designed in 32nm technology and simulated with HSPICE tools.

Author(s):  
Nakul C. Kubsad

Abstract: Full adder circuit is one among the fundamental and necessary digital part. The full adder is be a part of microprocessors, digital signal processors etc. It's needed for the arithmetic and logical operations. Full adder design enhancements are necessary for recent advancement. The requirement of an adder cell is to provide high speed, consume low power and provide high voltage swing. This paper analyses and compares 3 adders with completely different logic designs (Conventional, transmission gate & pseudo NMOS) for transistor count, power dissipation and delay. The simulation is performed in Cadence virtuoso tool with accessible GPDK – 180nm kit. Transmission gate full adder has sheer advantage of high speed, fewer space and also it shows higher performance in terms of delay. Keywords: Delay, power dissipation, voltage, transistor sizing.


2019 ◽  
Vol 11 (1) ◽  
pp. 80-87 ◽  
Author(s):  
Jitendra Kumar Saini ◽  
Avireni Srinivasulu ◽  
Renu Kumawat

The transformation from the development of enabling technology to mass production of consumer-centric semiconductor products has empowered the designers to consider characteristics like robustness, compactness, efficiency, and scalability of the product as implicit pre-cursors. The Carbon Nanotube Field Effect Transistor (CNFET) is the present day technology. In this manuscript, we have used CNFET as the enabling technology to design a 1-bit Full Adder (1b-FA16) with overflow detection. The proposed 1b-FA16 is designed using 16 transistors. Finally, the proposed 1b-FA16 is further used to design a Ripple Carry Adder (RCA), Carry Look Ahead Adder (CLA) circuit and RCA with overflow bit detection. Methods and Results: The proposed 1b-FA16 circuit was designed with CNFET technology simulated at 32 nm with a voltage supply of +0.9 V using the Cadence Virtuoso CAD tool. The model used is Stanford PTM. Comparison of the existing full adder designs with the proposed 1b-FA16 design was done to validate the improvements in terms of power, delay and Power Delay Product (PDP). Table 2, shows the results of comparison for the proposed 1b-FA16 with the existing full adder designs implemented using CNFET for parameters like power, delay and power delay product. Conclusion: It can be concluded that the proposed 1b-FA16 yielded better results as compared to the existing full adder designs implemented using CNFET. The improvement in power, delay and power delay product was approximately 11%, 9% and 24% respectively. Hence, the proposed circuit implemented using CNFET gives a substantial rate of improvements over the existing circuits.


Author(s):  
Mona Moradi

Adder core respecting to its various applications in VLSI circuits and<br />systems is considered as the most critical building block in microprocessors,<br />digital signal processors and arithmetic operations. Novel designs of a low<br />power and complexity Current Mode 1-bit Full Adder cell based on<br />CNTFET technology has been presented in this paper. Three major parts<br />construct their structures; 1) the first part that converts current to voltage; 2)<br />threshold detectors (TD); and 3) parallel paths to convey the output currents<br />flow. Adjusting threshold voltages which are significant factor for setting<br />threshold detectors switching point has been achieved by means of CNTFET<br />technology. It would bring significant improvements in adjusting threshold<br />voltages, regarding to its unique characterizations. Simple design, less<br />transistor counts and static power dissipation and better performance<br />comparing previous designs could be considered as some advantages of the<br />novel designs.


2016 ◽  
Vol 4 (2) ◽  
pp. 124-129
Author(s):  
Vikash Prasad ◽  
◽  
Debaprasad Das

Carbon Nanotube Field Effect Transistor (CNTFET) is one of the promising devices for future nanoscale technologies. In this paper, we have studied the drain characteristics of MOSFET-like CNTFETs for different device parameters like, channel length, diameter of CNT, and number of tubes. It is shown that these device parameters can be used to make important design decisions while designing nanoelectronic circuits. A buffer and ring oscillator circuits are designed using the MOSFET-like CNTFET and propagation delay, power, and power-delay-product (PDP) values are calculated and compared with the CMOS based designs. Also, the CNTFET technology based SRAM cell is compared with CMOS technology based SRAM in term of power consumption. We have shown that CNTFET can exhibit better performance in the nanoscale regime as compared to its CMOS counterparts.


2019 ◽  
Vol 14 (11) ◽  
pp. 1512-1522 ◽  
Author(s):  
Seyedehsomayeh Hatefinasab

Scaling down the size of transistor in the nanoscale reduces the power supply voltage, as a result, the design of high-performance nano-circuit at low voltage has been considered. Most of digital circuits are composed of different components which determine the performance of the entire digital circuits. With the improvement of these components, the digital circuits can be optimized. One of these components is full adder for which various structures have been proposed to improve its performance, among them the two novel full adder structures are based on Gate-Diffusion Input (GDI) structure and half-classical XOR/XNOR logic (SEMI XOR/XNOR) modules. In this paper, Carbon Nanotube Field Effect Transistor (CNTFET)-based low power full adders by using SEMI XOR logic style and GDI structure are presented. Due to the incomparable thermal and mechanical properties of the CNTFET, it can be the first alternative to substitute the metal oxide field effect transistors (MOSFET). The digital circuits have the better performance based on CNTFET. Therefore, the three proposed full adders in this paper are designed based on CNTFET technology with many merits, such as low power dissipation, less energy delay product (EDP), and high speed at various supply voltages, frequencies, temperatures, load capacitors, and the number of tubes. Moreover, these proposed full adders occupy the minimum area consumption and have better performance in comparison with previous standard full adders. All simulations are done by using the Synopsys HSPICE simulator in 32 nm-CNTFET technology and layout of all full adder circuits are presented on Electric.


2020 ◽  
Vol 24 (2) ◽  
Author(s):  
Avireni Srinivasulu ◽  
Jitendra Kumar Saini ◽  
Renu Kumawat

The VLSI based circuits often pose challenges in the form of various faults (such as transient faults, permanent faults, stuck-at-faults). These faults appear even after testing also. They occur because of reduction in the size of the circuit or during realtime implementation, as these faults are difficult to detect. It is very important to detect and rectify all such faults to make the system foolproof and achieve expected functionality. In this paper, 12 transistors based, full adder circuit (12T-FAC) using Carbon Nanotube Field Effect Transistor (CNFET) technology is proposed. The proposed design based on CNFET provides high fault resistance towards transient, permanent faults and works with least power, delay and power-delay product (PDP). Later, features like fault detection and correction circuit have been added in 12T-FAC. The final version of full adder circuit capable of correcting errors has been used in designing applications like multipliers. The proposed full adder circuit was designed with CNFET technology, simulated at 32 nm with supply voltage +0.9 V using the Cadence Virtuoso CAD tool. The model used is Stanford PTM.


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