scholarly journals High-Speed Serializer for a 64 GS s<sup>−1</sup> Digital-to-Analog Converter in a 28 nm Fully-Depleted Silicon-on-Insulator CMOS Technology

2018 ◽  
Vol 16 ◽  
pp. 99-108
Author(s):  
Daniel Widmann ◽  
Markus Grözing ◽  
Manfred Berroth
Keyword(s):  
High Speed ◽  
Average Power ◽  
Silicon On Insulator ◽  
Output Stage ◽  
Fully Depleted ◽  
Data Rates ◽  
Average Power Consumption ◽  
Digital To Analog ◽  
On Chip ◽  
28 Nm

Abstract. An attractive solution to provide several channels with very high data rates of tens of Gbit s−1 for digital-to-analog converters (DACs) in arbitrary waveform generators (AWGs) is to use a high speed serializer in front of the DAC. As data sources, on-chip memories, digital signal processors or field-programmable gate arrays can be used. Here, we present a serializer consisting of a 19 channel 16:1 multiplexer (MUX) for output data rates up to 64 Gbit s−1 per channel and a low skew (∼ 8.8 ps) two-phase frequency divider and clock distribution network that is completely realized in static CMOS logic. The circuit is designed in a 28 nm Fully-Depleted Silicon-on-Insulator (FD-SOI) technology and will be used in an 8 bit 64 GS s−1 DAC between the on-chip memory and the DAC output stage. Due to a four bits unary and four bits binary segmentation, a 19 channel MUX is required. Simulations on layout level reveal a data-dependent peak-to-peak jitter of less than 1.8 ps at the output of one MUX channel with a total average power consumption of approximately 1.15 W of the whole MUX and clock network.

A 31 GHz body-biased configurable power amplifier in 28 nm FD-SOI CMOS for 5 G applications

2020 ◽  
pp. 1-18
Author(s):  
Florent Torres ◽  
Eric Kerhervé ◽  
Andreia Cathelin ◽  
Magali De Matos
Keyword(s):  
Power Amplifier ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Silicon On Insulator ◽  
Oxide Semiconductor ◽  
Fully Depleted ◽  
Technology Roadmap ◽  
Wide Range ◽  
28 Nm ◽  
Soi Cmos

Abstract This paper presents a 31 GHz integrated power amplifier (PA) in 28 nm Fully Depleted Silicon-On-Insulator Complementary Metal Oxide Semiconductor (FD-SOI CMOS) technology and targeting SoC implementation for 5 G applications. Fine-grain wide range power control with more than 10 dB tuning range is enabled by body biasing feature while the design improves voltage standing wave ratio (VSWR) robustness, stability and reverse isolation by using optimized 90° hybrid couplers and capacitive neutralization on both stages. Maximum power gain of 32.6 dB, PAEmax of 25.5% and Psat of 17.9 dBm are measured while robustness to industrial temperature range and process spread is demonstrated. Temperature-induced performance variation compensation, as well as amplitude-to-phase modulation (AM-PM) optimization regarding output power back-off, are achieved through body-bias node. This PA exhibits an International Technology Roadmap for Semiconductors figure of merit (ITRS FOM) of 26 925, the highest reported around 30 GHz to authors' knowledge.

scholarly journals Performance Analysis of a Low Power High Speed Hybrid Full Adder Circuit and Full Subtractor Circuit

2021 ◽  
Vol 12 (3) ◽  
pp. 3037-3045
Author(s):  
M. Naga Gowtham Et.al
Keyword(s):  
High Speed ◽  
Supply Voltage ◽  
Average Power ◽  
Full Adder ◽  
Digital Circuit ◽  
Oxide Semiconductor ◽  
Transmission Gate ◽  
Average Power Consumption ◽  
Pass Transistor ◽  
Pass Transistor Logic

In this paper, a hybrid 1-bit adder and 1-bit Subtractor designs are implemented. The hybrid adder circuit is constructed using CMOS (complementary metal oxide semiconductor) logic along with pass transistor logic. The design can be extended 16 and 32 bits lately. The proposed full adder circuit is compared with the existing conventional adders in terms of power, delay and area in order to obtain a better circuit that serves the present day needs of people. The existing 1-bit hybrid adder uses EXNOR logic combined with the transmission gate logic. For a supply voltage of 1.8V the average power consumption (4.1563 µW) which is extremely low with moderately low delay (224 ps) resulting because of the deliberate incorporation of very weak CMOS inverters coupled with strong transmission gates. At 1.2V supply the power and delay were recorded to be 1.17664 µW and 91.3 ps. The design was implemented using 1-bit which can also be extended into a 32-bit design later. The designed implementation offers a better performance in terms of power and speed compared to the existing full adder design styles. The circuits were implemented in DSCH2 and Microwind tools respectively. The parameters such as power, delay, layout area and speed of the proposed circuit design is compared with pass transistor logic, adiabatic logic, transmission gate adder and so on. The circuit is also designed with a decrease in transistors in order to get the better results. Full Subtractor, a combinational digital circuit which performs 1-bit subtraction with borrow in is designed as a part of this project. The main aim behind this part of the project is to design a 1-bit full Subtractor using CMOS technology with reduced number of transistors and hence the efficiency in terms of area, power and speed have been calculated is designed using 8,10,15and 16 transistors. The parameters were calculated in each case and the results have been tabulated.

scholarly journals Performance Analysis of a Low Power High Speed Hybrid Full Adder Circuit and Full Subtractor Circuit

2021 ◽  
Vol 12 (5) ◽  
pp. 92-100
Author(s):  
M. Naga Gowtham, P.S Hari Krishna Reddy, K Jeevitha, K Hari Kishore, E Raghuveera, Shaik Razia
Keyword(s):  
High Speed ◽  
Supply Voltage ◽  
Average Power ◽  
Full Adder ◽  
Digital Circuit ◽  
Oxide Semiconductor ◽  
Transmission Gate ◽  
Average Power Consumption ◽  
Pass Transistor ◽  
Pass Transistor Logic

In this paper, a hybrid 1-bit adder and 1-bit Subtractor designs are implemented. The hybrid adder circuit is constructed using CMOS (complementary metal oxide semiconductor) logic along with pass transistor logic. The design can be extended 16 and 32 bits lately. The proposed full adder circuit is compared with the existing conventional adders in terms of power, delay and area in order to obtain a better circuit that serves the present day needs of people. The existing 1-bit hybrid adder uses EXNOR logic combined with the transmission gate logic. For a supply voltage of 1.8V the average power consumption (4.1563 µW) which is extremely low with moderately low delay (224 ps) resulting because of the deliberate incorporation of very weak CMOS inverters coupled with strong transmission gates. At 1.2V supply the power and delay were recorded to be 1.17664 µW and 91.3 ps. The design was implemented using 1-bit which can also be extended into a 32-bit design later. The designed implementation offers a better performance in terms of power and speed compared to the existing full adder design styles. The circuits were implemented in DSCH2 and Microwind tools respectively. The parameters such as power, delay, layout area and speed of the proposed circuit design is compared with pass transistor logic, adiabatic logic, transmission gate adder and so on. The circuit is also designed with a decrease in transistors in order to get the better results. Full Subtractor, a combinational digital circuit which performs 1-bit subtraction with borrow in is designed as a part of this project. The main aim behind this part of the project is to design a 1-bit full Subtractor using CMOS technology with reduced number of transistors and hence the efficiency in terms of area, power and speed have been calculated is designed using 8,10,15and 16 transistors. The parameters were calculated in each case and the results have been tabulated.

Designing of Low-Power High-Speed Noise Immune CNTFET 1-Trit Unbalanced Ternary Subtractor

2021 ◽  
Author(s):  
Yogesh Shrivastava ◽  
Tarun Kumar Gupta
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Noise Analysis ◽  
Average Power ◽  
Noise Margin ◽  
Average Power Consumption ◽  
Effect Transistor ◽  
Power Delay Product ◽  
Static Noise ◽  
Made In

Ternary logic has been demonstrated as a superior contrasting option to binary logic. This paper presents a ternary subtractor circuit in which the input signal is converted into binary. The proposed design is implemented using Carbon Nanotube Field Effect Transistor (CNTFET), a forefront innovation. A correlation has been made in the proposed design on parameters like Power-Delay Product (PDP), Energy Delay Product (EDP), average power consumption, delay and static noise margin. Every one of these parameters is obtained by simulating the circuits on the HSPICE simulator. The proposed design indicates an improvement of 60.14%, 59.34%, 74.98% and 84.28%, respectively, in power consumption, delay, PDP and EDP individually in correlation with recent designs. The increased carbon nanotubes least affect the proposed subtractor design. In noise analysis, the proposed design outperformed all the existing designs.

Study and Reduction of Variability in 28 nm Fully Depleted Silicon on Insulator Technology

2016 ◽  
Vol 12 (1) ◽  
pp. 64-73 ◽  
Author(s):  
Zhaopeng Wei ◽  
Gilles Jacquemod ◽  
Philippe Lorenzini ◽  
Frederic Hameau ◽  
Emeric de Foucauld ◽  
...  
Keyword(s):  
Silicon On Insulator ◽  
Fully Depleted ◽  
Silicon On Insulator Technology ◽  
28 Nm

Energy Study for 28 nm Fully Depleted Silicon-On-Insulator Devices

2016 ◽  
Vol 12 (1) ◽  
pp. 58-63
Author(s):  
Rida Kheirallah ◽  
Gilles Ducharme ◽  
Nadine Azemard
Keyword(s):  
Silicon On Insulator ◽  
Fully Depleted ◽  
28 Nm

Low-power 8-bit 5-GS/s digital-to-analog converter for multi-gigabit wireless transceivers

2012 ◽  
Vol 4 (3) ◽  
pp. 275-282 ◽  
Author(s):  
Behnam Sedighi ◽  
Mahdi Khafaji ◽  
Johann Christoph Scheytt
Keyword(s):  
Low Power ◽  
High Speed ◽  
Wireless Transceivers ◽  
Digital To Analog Converter ◽  
Bicmos Technology ◽  
Analog Converter ◽  
Sige Bicmos ◽  
Digital To Analog ◽  
On Chip ◽  
Binary Weighted

We present a method to realize a low-power and high-speed digital-to-analog converter (DAC) for system-on-chip applications. The new method is a combination of binary-weighted current cells and R-2R ladder and is specially suited for modern BiCMOS technologies. A prototype 5 GS/s DAC is implemented in 0.13 μm SiGe BiCMOS technology. The DAC dissipates 26 mW and provides an SFDR higher than 48 dB for output frequencies up to 1 GHz.

scholarly journals A Scatter-and-Gather Spiking Convolutional Neural Network on a Reconfigurable Neuromorphic Hardware

2021 ◽  
Vol 15 ◽  
Author(s):  
Chenglong Zou ◽  
Xiaoxin Cui ◽  
Yisong Kuang ◽  
Kefei Liu ◽  
Yuan Wang ◽  
...  
Keyword(s):  
Neural Networks ◽  
Large Scale ◽  
Average Power ◽  
Time Step ◽  
Mapping Algorithm ◽  
Learning Tasks ◽  
Main Challenge ◽  
Neuromorphic Hardware ◽  
Average Power Consumption ◽  
On Chip

Artificial neural networks (ANNs), like convolutional neural networks (CNNs), have achieved the state-of-the-art results for many machine learning tasks. However, inference with large-scale full-precision CNNs must cause substantial energy consumption and memory occupation, which seriously hinders their deployment on mobile and embedded systems. Highly inspired from biological brain, spiking neural networks (SNNs) are emerging as new solutions because of natural superiority in brain-like learning and great energy efficiency with event-driven communication and computation. Nevertheless, training a deep SNN remains a main challenge and there is usually a big accuracy gap between ANNs and SNNs. In this paper, we introduce a hardware-friendly conversion algorithm called “scatter-and-gather” to convert quantized ANNs to lossless SNNs, where neurons are connected with ternary {−1,0,1} synaptic weights. Each spiking neuron is stateless and more like original McCulloch and Pitts model, because it fires at most one spike and need be reset at each time step. Furthermore, we develop an incremental mapping framework to demonstrate efficient network deployments on a reconfigurable neuromorphic chip. Experimental results show our spiking LeNet on MNIST and VGG-Net on CIFAR-10 datasetobtain 99.37% and 91.91% classification accuracy, respectively. Besides, the presented mapping algorithm manages network deployment on our neuromorphic chip with maximum resource efficiency and excellent flexibility. Our four-spike LeNet and VGG-Net on chip can achieve respective real-time inference speed of 0.38 ms/image, 3.24 ms/image, and an average power consumption of 0.28 mJ/image and 2.3 mJ/image at 0.9 V, 252 MHz, which is nearly two orders of magnitude more efficient than traditional GPUs.

scholarly journals CMOS RF Transmitters with On-Chip Antenna for Passive RFID and IoT Nodes

Electronics ◽  
2019 ◽  
Vol 8 (12) ◽  
pp. 1448 ◽  
Author(s):  
Massimo Merenda ◽  
Demetrio Iero ◽  
Francesco G. Della Corte
Keyword(s):  
Average Power ◽  
Monolithically Integrated ◽  
Rf Transmitters ◽  
Sufficient Power ◽  
Average Power Consumption ◽  
On Chip Antenna ◽  
Data Transmission System ◽  
On Chip ◽  
Loop Antennas ◽  
Passive Rfid

The performances of two RF transmitters, monolithically integrated with their antennas on a single CMOS microchip fabricated in a standard 0.35 µm process, are presented. The usage of these architectures in the Internet of Things (IoT) paradigm is envisioned, as part of a custom conceived data transmission system. The implemented circuits use two different directly on–off keying (OOK) modulated oscillator topologies whose outputs are employed to feed two loop antennas. The powering of both transmitters is duty-cycled for reducing the average power consumption to a few tenths of a microwatt, allowing the usage as low-power transmitters for IoT nodes. The integrated loop antennas radiate sufficient power for a few meters’ communication range. The OOK transmitted signal can be easily detected using a commercial receiver.

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