scholarly journals Design of Carry Select Adder using BEC and Common Boolean Logic

2022 ◽  
pp. 5-9
Author(s):  
Syed Mustafaa M ◽  
◽  
Sathish M ◽  
Nivedha S ◽  
Magribatul Noora A K ◽  
...  
Keyword(s):  
Power Consumption ◽  
Dynamic Method ◽  
Boolean Logic ◽  
Square Root ◽  
Large Area ◽  
Carry Select Adder ◽  
Great Scope

Carry Select Adder (CSLA) is known to be the fastest adder among the conventional adder structure, which uses multiple narrow adders. CSLA has a great scope of reducing area, power consumption, speed and delay. From the structure of regular CSLA using RCA, it consumes large area and power. This proposed work uses a simple and dynamic Gate Level Implementation which reduces the area, delay, power and speed of the regular CSLA. Based on a modified CSLA using BEC the implementation of 8-b, 16-b, 32-b square root CSLA (SQRT CSLA) architecture have been developed. In order to reduce the area and power consumption in a great way we proposed a design using binary to excess 1 converter (BEC). This paper proposes an dynamic method which replaces a BEC using Common Boolean Logic.

scholarly journals FPGA-Based Synthesis of High-Speed Hybrid Carry Select Adders

2015 ◽  
Vol 2015 ◽  
pp. 1-13 ◽  
Author(s):  
V. Kokilavani ◽  
K. Preethi ◽  
P. Balasubramanian
Keyword(s):  
High Speed ◽  
Boolean Logic ◽  
The Other ◽  
Square Root ◽  
Verilog Hdl ◽  
Other Hand ◽  
Carry Select Adder

Carry select adder is a square-root time high-speed adder. In this paper, FPGA-based synthesis of conventional and hybrid carry select adders are described with a focus on high speed. Conventionally, carry select adders are realized using the following: (i) full adders and 2 : 1 multiplexers, (ii) full adders, binary to excess 1 code converters, and 2 : 1 multiplexers, and (iii) sharing of common Boolean logic. On the other hand, hybrid carry select adders involve a combination of carry select and carry lookahead adders with/without the use of binary to excess 1 code converters. In this work, two new hybrid carry select adders are proposed involving the carry select and section-carry based carry lookahead subadders with/without binary to excess 1 converters. Seven different carry select adders were implemented in Verilog HDL and their performances were analyzed under two scenarios, dual-operand addition and multioperand addition, where individual operands are of sizes 32 and 64-bits. In the case of dual-operand additions, the hybrid carry select adder comprising the proposed carry select and section-carry based carry lookahead configurations is the fastest. With respect to multioperand additions, the hybrid carry select adder containing the carry select and conventional carry lookahead or section-carry based carry lookahead structures produce similar optimized performance.

scholarly journals MINIATURE IMPROVED CARRY SELECT ADDER WITH ADVANCE FEATURES AND POWER REQUIREMENTS

2014 ◽  
pp. 99-103
Author(s):  
D. KRISHNA NAIK ◽  
DR V. VIJAYALAKSHMI
Keyword(s):  
Power Consumption ◽  
Data Processing ◽  
Arithmetic Functions ◽  
Square Root ◽  
Carry Select Adder ◽  
Overall Efficiency ◽  
Better Than

In most of the data processing processors to perform arithmetic functions Carry Select Adder (CSLA) is used as this is one of the fastest adders. In order to increase the overall efficiency of the processor we can reduce the area and power consumption of the CSLA of processors. Based on this premise we can modify the regular SQRT CSLA architecture as 8-, 16-, 32-, and 64-b square-root CSLA (SQRT CSLA) architecture. The proposed design has reduced area and power as compared with the regular SQRT CSLA with only a slight increase in the delay. This work evaluates the performance of the proposed designs in terms of delay, area, power. The results analysis shows that the proposed CSLA structure is better than the regular SQRT CSLA.

ASIC and FPGA Comparative Study for IoT Lightweight Hardware Security Algorithms

2019 ◽  
Vol 28 (12) ◽  
pp. 1930009 ◽  
Author(s):  
Nagham Samir ◽  
Abdelrahman Sobeih Hussein ◽  
Mohaned Khaled ◽  
Ahmed N. El-Zeiny ◽  
Mahetab Osama ◽  
...  
Keyword(s):  
Power Consumption ◽  
Comparative Study ◽  
Authenticated Encryption ◽  
Wireless Data ◽  
Large Area ◽  
Chip Design ◽  
Iot Applications ◽  
Main Requirement ◽  
Wireless Data Transmission ◽  
The Internet Of Things

Data security, privacy and authenticity are crucial in wireless data transmission. Low power consumption is the main requirement for any chip design targeting the Internet of Things (IoT) applications. In this research paper, a comparative study of eight authenticated encryption and decryption algorithms, selected from the “Competition for Authenticated Encryption: Security, Applicability and Robustness” (CAESAR), namely, ACORN, ASCON, CLOC, JOLTIK, MORUS, PRIMATEs, SCREAM and SILC, is presented. The FPGA and ASIC implementations of these eight algorithms are synthesized, placed and routed. Power, area, latency and throughput are measured for all algorithms. All results are analyzed to determine the most suitable algorithm for IoT applications. These results show that ACORN algorithm exhibits the lowest power consumption of the eight studied at the expense of lower throughput and higher latency. MORUS algorithm gives the highest throughput among the eight selected algorithms at the expense of large area utilization.

Wires, switches, and wiring. A route toward a chemically assembled electronic nanocomputer

2000 ◽  
Vol 72 (1-2) ◽  
pp. 11-20 ◽  
Author(s):  
James R. Heath
Keyword(s):  
Power Consumption ◽  
Hierarchical Organization ◽  
Boolean Logic ◽  
High Yield ◽  
Collaborative Effort ◽  
Hewlett Packard ◽  
Field Programmable ◽  
Read Only Memory ◽  
Logic Structures ◽  
Molecular Compounds

A Boolean logic, nonreversible computing machine should, in principle, be capable of 10 18 bit operations per second at a power consumption of 1 W. In order to build such a machine that can even approach this benchmark for efficiency, the development of a robust quantum-state switch capable of ambient operation, as well as a bottom–up manufacturing technology, will be necessary. My group, in collaboration with Hewlett Packard, has developed much of the architecture for such a machine, which we call a chemically assembled electronic nanocomputer (CAEN). More recently, in a collaborative effort with Fraser Stoddart's group at UCLA, we have begun to build it. The fundamental unit of the machine is a field-programmable molecular switch, and the fundamental architecture is a hierarchical organization of wire/switch lattices called crossbars. Electronically, singly configurable molecular-based switch devices based on rotaxane molecular compounds have been fabricated in high yield. These switches were used to construct simple molecular-based logic structures and read-only memory elements.

An Area and Speed Efficient Square Root Carry Select Adder Using Optimized Logic Units

2015 ◽  
Author(s):  
Dr. P.Bhaskara Reddy ◽  
S.V.S. Prasad ◽  
K. Ananda Kumar
Keyword(s):  
Square Root ◽  
Carry Select Adder

Design of High-Speed Desensitized FIR Filter Employing Reduced Complexity SQRT Carry Select Adder

2019 ◽  
Vol 8 (10) ◽  
pp. 4288-4296
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Filter Design ◽  
Fir Filter ◽  
Simulation Tools ◽  
Booth Multiplier ◽  
Ripple Carry Adder ◽  
Carry Select Adder ◽  
Reduced Complexity ◽  
Fir Filter Design

In this research, a highly efficient desensitized FIR filter is designed to enhance the performance of digital filtering operation. With regard to FIR filter design, Multiplication and Accumulation component (MAC) forms the core processing entity. Half-band filters employing Ripple Carry Adder (RCA) based MAC structures have a sizeable number of logical elements, leading to high delay and high power consumption. To minimize these issues, a modified Booth multiplier encompassing SQRT Carry Select Adder (CSLA) based MAC component is proposed for the desensitized filter with reduced coefficients and employing lesser number of logical elements forgiving optimum performance with respect to delay and power consumption. The suggested FIR filter is simulated and assessed using EDA simulation tools from Modelsim 6.3c and Xilinx ISE. The results obtained from the proposed Desensitized FIR filter employing the modified booth multiplier with reduced complexity based SQRT CSLA show encouraging signs with respect to 12.08% reduction in delay and 2.2% reduction in power consumption when compared with traditional RCA based digital FIR filter.

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