An Efficient Design of 16 Bit MAC Unit using Vedic Mathematics

2021 ◽  
pp. 1-4
Author(s):  
N. Manoj Kumar ◽  
◽  
G. Saravanan ◽  
D. Shyam Ganesh ◽  
S. Kanimozi ◽  
...  
Keyword(s):  
Digital Signal ◽  
Digital Signal Processors ◽  
Square Root ◽  
Efficient Design ◽  
Verilog Hdl ◽  
Vedic Mathematics ◽  
Vedic Multiplier ◽  
Game Plan ◽  
Signal Processors

Duplicate and Accumulate (MAC) is one of the central practices utilized absolutely in signal- controlling and different applications. The multiplier is the major piece of Digital Signal Processors (DSPs). Its cutoff spins around power, LUT use, and surrender pick the presence of a DSP. In like way, there is a need to sort out the drive and give up fit multiplier. In this paper, a 16-digit MAC unit is proposed to utilize an 8-cycle Vedic multiplier and pass on a save snake. A relationship with the current 8-cycle Vedic multiplier utilizing Square-Root (SQR) Carry-select snake (CSLA) is introduced. It is isolated and a standard pack multiplier. The whole technique is done in Verilog HDL. Blend and redirections were finished utilizing Xilinx InDesign Suite 14.5. The proposed game plan accomplishes fundamental improvement in region and suspension. In like manner, an abatement in power around 9.5% is refined.

scholarly journals A Fresh Design of Power Effective Adapted Vedic Multiplier for Modern Digital Signal Processors

2021 ◽  
Author(s):  
K Gavaskar ◽  
D Malathi ◽  
G Ravivarma ◽  
V Krithika Devi ◽  
M Megala ◽  
...  
Keyword(s):  
Mathematical Practice ◽  
Digital Signal ◽  
Structure Design ◽  
Digital Signal Processors ◽  
Parameter Analysis ◽  
Vedic Mathematics ◽  
Multiplication Process ◽  
Vedic Multiplier ◽  
Wallace Tree Multiplier ◽  
Signal Processors

Abstract The Multiply Accumulate (MAC) unit constructed using antiquated Vedic mathematical practice and the efficiency of the vertical and transversely of Vedic approach for multiplication, which gives a distinction in genuine cycle of Multiplier itself. Vedic-Mathematics is depend on 16-Sutras, in that Urdhva-Triyakbhyam (UT) more productive one. It literally means vertical and cross wise operations. It eliminates unwanted multiplication and allows the parallel creation of partial products and addition steps. The adders are utilized to append the partial-product generated in the Vedic mathematics methodology to drops the combinational lag. MAC is an essential unit in the digital signal processors, to show the characters like speed, power as well as area. Hence, finer multiplier plans are to increase the order of the system. The Modified sum product algorithm based Vedic multiplier is one such promising solution. It has a rapid multiplication process and reaches a less calculation complexity above its traditional multiplier. Array multiplier, Baugh-Wooley multiplier, Wallace-tree multiplier and Vedic multiplier were created in the existing work. In proposed work Vedic multiplier, using modified sum product algorithm was designed. The structure design coded in verilog and parameter analysis was done in Xilinx. The parameters like delay as well as power were compare between existing and proposed. When comparing with different multiplier with our proposed work delay get reduced. Comparing with existing multiplier the proposed 4x4 Vedic multiplier have 49.12% reduction in delay. Comparing with existing multiplier the proposed Vedic 4x4 multiplier have 42.51% reduction in power.

scholarly journals Complex Number Vedic Multiplier and its Implementation in a Filter

2018 ◽  
Vol 7 (2.24) ◽  
pp. 336
Author(s):  
N Saraswathi ◽  
Lokesh Modi ◽  
Aatish Nair
Keyword(s):  
Complex Number ◽  
Digital Signal ◽  
Digital Signal Processors ◽  
Complex Numbers ◽  
Fast Speed ◽  
Vedic Multiplier ◽  
X 32 ◽  
Signal Processors ◽  
Complex Multiplier ◽  
Mathematical Process

Complex numbers multiplication is a fundamental mathematical process in systems like digital signal processors (DSP). The main     objective of complex number multiplication is to perform operations at lightning fast speed with less intake of power. In this paper, the best possible architecture is designed for a Real vedic multiplier based on the ancient Indian mathematical procedure known as URDHVA TIRYAKBHYAM SUTRA i.e. the structure of a MxM Vedic real multiplier architecture is developed. Then, a Vedic real multiplier solution of a complex multiplier is presented and its simulation results are obtained. The MxM Vedic real multiplier architecture, architecture of the Real Vedic  multiplier solution for 32 x 32 bit complex numbers multiplication of complex multiplier and the architecture of a FIR filter has been code in Verilog and implementation is done through Modelsim 5.6 and Xilinx ISE 7.1 navigator. 

High Speed Vedic Multiplier for Digital Signal Processors

2009 ◽  
Vol 55 (6) ◽  
pp. 282 ◽  
Author(s):  
Ramesh Pushpangadan ◽  
Vineeth Sukumaran ◽  
Rino Innocent ◽  
Dinesh Sasikumar ◽  
Vaisak Sundar
Keyword(s):  
High Speed ◽  
Digital Signal ◽  
Digital Signal Processors ◽  
Vedic Multiplier ◽  
Signal Processors

scholarly journals A Review on IEEE-754 Standard Floating Point Multiplier using Vedic Mathematics

2021 ◽  
Vol 9 (VI) ◽  
pp. 1300-1303
Author(s):  
Rajesh Deokate
Keyword(s):  
Digital Signal ◽  
Digital Signal Processors ◽  
Floating Point ◽  
Standard Format ◽  
Processing Elements ◽  
Vedic Mathematics ◽  
One Step ◽  
Basic Functions ◽  
Step Generation ◽  
Signal Processors

The fundamental and the core of all the Digital Signal Processors (DSPs) are its multipliers and the speed of the DSPs is mainly determined by the speed of its multiplier. IEEE floating point format is a standard format used in all processing elements since Binary floating point numbers multiplication is one of the basic functions used in digital signal processing (DSP) application. In this work VHDL implementation of Floating Point Multiplier using Vedic mathematics is carried out. The Urdhva Tiryakbhyam sutra (method) was selected for implementation since it is applicable to all cases of multiplication. Multiplication of two no’s using Urdhva Tiryakbhyam sutra is performed by vertically and crosswise. The feature is any multi-bit multiplication can be reduced down to single bit multiplication and addition using this method. On account of these formulas, the carry propagation from LSB to MSB is reduces due to one step generation of partial product.

An Efficient Design for Area-Efficient Truncated Adaptive Booth Multiplier for Signal Processing Applications

2020 ◽  
pp. 2150037
Author(s):  
S. Radhakrishnan ◽  
Rakesh Kumar Karn ◽  
T. Nirmalraj
Keyword(s):  
Signal Processing ◽  
Digital Signal ◽  
Partial Product ◽  
Efficient Design ◽  
Verilog Hdl ◽  
Booth Multiplier ◽  
Vedic Multiplier ◽  
Product Array ◽  
Processing Architecture ◽  
State Of Art

In digital signal processing (DSP), the most valuable elements of processing architecture are multiplier. The conventional partial products array is to create extra rows and columns. Generally, the fixed multiplication products are truncated to [Formula: see text] bits. In this paper, we introduced an adaptive booth multiplier concept, which is based on truncated multiplication procedure. The extra partial product array is to create the complexities. In the higher order of partial product array, the deletion of LSB and the nongeneration of initial products are achieved. We added compensation bits at the appropriate retained bit position to minimize the error due to nongeneration and omission. Here, our proposed work is used to reduce the overhead and the complexity of partial product array. The proposed concept architecture is implemented in Verilog HDL software; also the design of RTL is manufactured. For experimental work, the bit multiplication of [Formula: see text] with 8, 10, 12, 14 and 16 bits is used. The proposed method of truncated based adaptive booth encoding has shown the lower value results of area, delay and power consumption. The error performances are executed by various error normalizations. Finally, the proposed concept performance is checked with various state-of-art multiplier methodologies such as carry width multiplier, Vedic multiplier, voltage-mode multiplier and Wallace multiplier. In every bit value, the proposed booth encoding multiplier delivers better and optimal performance result.

scholarly journals A Fresh Design of Power Effective Adapted Vedic Multiplier for Modern Digital Signal Processors

2021 ◽  
Author(s):  
K. Gavaskar ◽  
D. Malathi ◽  
G. Ravivarma ◽  
V. Krithika Devi ◽  
M. Megala ◽  
...  
Keyword(s):  
Digital Signal ◽  
Digital Signal Processors ◽  
Vedic Multiplier ◽  
Signal Processors

scholarly journals Delay Efficient Vedic Multiplier for DSP

2019 ◽  
Vol 8 (9S) ◽  
pp. 499-501
Keyword(s):  
Digital Signal ◽  
Digital Signal Processors ◽  
Vedic Multiplier ◽  
Ripple Carry Adder ◽  
Parallel Prefix ◽  
Minimum Delay ◽  
Signal Processors ◽  
Prefix Adders ◽  
Dsp Applications

Multipliers are very essential blocks in any arithmetic and logic unit, accumulators and Digital signal processors. Due to the enlarging check on delay, design of faster multipliers is desired. Amidst numerous multipliers, Vedic multipliers are favored for their speed of operation. There are sixteen sutras in Vedic mathematics out of which four are multiplication techniques. “URDHVA TIRYAKBHYAM” is the most efficient vedic multiplication technique in terms of speed. In this paper we aim to develop a multiplier using Ripple Carry Adder and parallel prefix adders which carry out the “URDHVA TIRYAKBHYAM” sutra with improved speed of operation by providing the minimum delay for the multiplication of numbers regardless of their bit sizes. A vast majority of the engineering domain consists of ubiquitous technologies like DSP. As it is one of the most rapid growing technologies of the 21st Century, it faces challenges and improvisation at each step. Engineers are working diligently to improve the quality of Digital Signal processors and major breakthroughs are being made at a very good rate. Proposed multiplier could be applied for such DSP applications. Verilog language has been used for the coding. Xilinx Vivado Tool is used for synthesis and Model Sim 5.4 has been used for simulation.

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