Monolithic 3D Inverter with Interface Charge: Parameter Extraction and Circuit Simulation

We have simulated a monolithic three-dimensional inverter (M3DINV) structure by considering the interfacial trap charges generated thermally during the monolithic three-dimensional integration process. We extracted the SPICE model parameters from M3DINV structures with two types of inter-layer dielectric thickness TILD (=10, 100 nm) using the extracted interface trap charge distribution of the previous study. Logic circuits, such as inverters (INVs), ring oscillators (ROs), a 2 to 1 multiplexer (MUX), and D flip-flop and 6-transistor static random-access memory (6T SRAM) containing M3DINVs, were simulated using the extracted model parameters, and simulation results both with and without interface trap charges were compared. The extracted model parameters reflected current reduction, threshold voltage increase, and subthreshold swing (SS) degradation due to the interface trap charge. HSPICE simulation results of the fanout-3 (FO3) ring oscillator considering the interface trap charges showed a 20% reduction in frequency and a 30% increase in propagation delay compared to those without the interface trap charges. The propagation delays of the 2 × 1 MUX and D flip-flop with the interface trap charges were approximately 78.2 and 39.6% greater, respectively, than those without the interface trap charges. The retention static noise margin (SNM) of the SRAM increased by 16 mV (6.4%) and the read static noise margin (SNM) of SRAM decreased by 43 mV (35.8%) owing to the interface trap charge. The circuit simulation results revealed that the propagation delay increases owing to the interface trap charges. Therefore, it is necessary to fully consider the propagation delay of the logic circuit due to the generated interface trap charges when designing monolithic 3D integrated circuits.

Steep Subthreshold Swing and Enhanced Illumination Stability InGaZnO Thin-Film Transistor by Plasma Oxidation on Silicon Nitride Gate Dielectric

In this paper, an InGaZnO thin-film transistor (TFT) based on plasma oxidation of silicon nitride (SiNx) gate dielectric with small subthreshold swing (SS) and enhanced stability under negative bias illumination stress (NBIS) have been investigated in detail. The mechanism of the high-performance InGaZnO TFT with plasma-oxidized SiNx gate dielectric was also explored. The X-ray photoelectron spectroscopy (XPS) results confirmed that an oxygen-rich layer formed on the surface of the SiNx layer and the amount of oxygen vacancy near the interface between SiNx and InGaZnO layer was suppressed via pre-implanted oxygen on SiNx gate dielectric before deposition of the InGaZnO channel layer. Moreover, the conductance method was employed to directly extract the density of the interface trap (Dit) in InGaZnO TFT to verify the reduction in oxygen vacancy after plasma oxidation. The proposed InGaZnO TFT with plasma oxidation exhibited a field-effect mobility of 16.46 cm2/V·s, threshold voltage (Vth) of −0.10 V, Ion/Ioff over 108, SS of 97 mV/decade, and Vth shift of −0.37 V after NBIS. The plasma oxidation on SiNx gate dielectric provides a novel approach for suppressing the interface trap for high-performance InGaZnO TFT.

Investigation on the interface trap characteristics in a p-channel GaN MOSFET through temperature-dependent subthreshold slope analysis

In this paper, a simple method based on subthreshold slopes was proposed to investigate the interface trap characteristics in a p-channel GaN MOSFET with a p-GaN/AlGaN/GaN structure on Si. The energy distribution of the interface trap density has been extracted from the analysis of the transfer characteristics in the subthreshold region of operation. The interface trap densities and respective energy distribution at both room temperature and 150 ℃ were also calculated from the ac conductance measurements at corresponding applied biases. Both characterization methods show similar results of trap densities and energy levels.