Logic Design and Power Optimization of Floating-Point Multipliers

Under IEEE-754 standard, for the current situation of excessive time and power consumption of multiplication operations in single-precision floating-point operations, the expanded boothwallace algorithm is used, and the partial product caused by booth coding is rounded and predicted with the symbolic expansion idea, and the partial product caused by single-precision floating-point multiplication and the accumulation of partial products are optimized, and the flowing water is used to improve the throughput. Based on this, a series of verification and synthesis simulations are performed using the SMIC-7 nm standard cell process. It is verified that the new single-precision floating-point multiplier can achieve a smaller power share compared to the conventional single-precision floating-point multiplier.

Yield and leakage current of organic thin-film transistor logic gates toward reliable and low-power operation of large-scale logic circuits for IoT nodes

This paper reports on a strategy for yield improvement and static leakage current reduction by using a standard cell design for large-scale organic thin-film transistor (OTFT) circuits. Printable or flexible devices are suitable for IoT nodes, and digital OTFT circuits comprise the peripheral circuits of such devices. Sufficiently high yields and low static power consumptions are essential for battery operations of IoT nodes having functional digital circuits. Our design method to address the weak n-type OTFT on-current results in improved logic gate yields without any cell area increase. We improved the yield of the inverter, NAND, and NOR gates using a standard cell design, and achieved a 100%yield for the inverter and NOR gates and 88%yield for the NAND gates. Signal propagations with rail-to-rail operation were measured on test chips. Leakage currents of 585 pA and 2.94 nA were achieved for the inverter and NOR gates, respectively.