A 2.5-GS/s Four-Way-Interleaved Ringamp-Based Pipelined-SAR ADC with Digital Background Calibration in 28-nm CMOS

A 2.5-GS/s 12-bit four-way time-interleaved pipelined-SAR ADC is presented in 28-nm CMOS. A bias-enhanced ring amplifier is utilized as the residue amplifier to achieve high bandwidth and excellent power efficiency compared with a traditional operational amplifier. A high linearity front-end is proposed to alleviate the non-linearity of the diode for ESD protection in the input PAD. The embedded input buffer can suppress the kickback noise at high input frequencies. A blind background calibration based on digital-mixing is used to correct the mismatches between channels. Additionally, an optional neural network calibration is also provided. The prototype ADC achieves a low-frequency SNDR/SFDR of 51.0/68.0 dB, translating a competitive FoMw of 0.48 pJ/conv.-step at 250 MHz input running at 2.5 GS/s.

Research on temperature sensitivity of Single-event Transient pulse width in 28-nm bulk technology

The influence of temperature on single-event transient (SET) pulse width has always been a hot issue in the field of anti-irradiation. Based on 3D-TCAD simulation, the temperature sensitivity of the SET pulse width of 28-nm bulk devices has been studied. The simulation results show that the electrical characteristics of the device shows an anti-temperature effect, but the worst case of SET pulse width still occurs at high temperature rather than low temperature. The influence of the triple-well structure on the temperature sensitivity of the SET pulse width has also been studied. The N+ deep well can significantly increase the SET pulse width when hitting NMOS device and enhance the temperature sensitivity of the SET pulse width. The research content of this article will provide reference for the design of radiation resistant chip.

A 4.32-ps precision Time-to-Digital Convertor using multisampling wave union method on a 28-nm FPGA

In this paper, a fully implemented field programmable gate array (FPGA) based time-to-digital converter (TDC) using multisampling wave union method (MSWU) is proposed to get higher measurement precision with lower resource utilization. Different from the previously published works based on wave union methods, an inverter-chain-based wave launcher is introduced to generate more low-jitter edges in the same operation range. Meanwhile, a new de-bubble solution combining with offline bin alignment and online bin sorting is applied to eliminate severe bubbles in FPGAs of advanced manufacturing technologies. The proposed TDCs are verified on a Virtex-7 (28 nm) of FPGA development board VC707. According to test results, the average measurement precision and mean resolution reach 4.32 ps and 0.82 ps, respectively with [-0.98;3.43] LSB DNL and [-6.06;34.1] LSB INL. A complete TDC channel only uses 831 D-type flip-flops (DFFs), 1305 look-up tables (LUTs) and 6 block random access memories (BRAMs) of 36k bits.

Vernier time-to-digital converter with ring oscillators for in-pixel time-of-arrival and time-over-threshold measurement in 28 nm CMOS

The paper describes a design of a prototype chip in 28 nm CMOS technology, consisting of 8 × 4 pixels with 50 μm pitch, dedicated for the precise measurement of Time-of-Arrival (ToA) and Time-over-Threshold (ToT) with a resolution within the picosecond range. To address this requirement, in-pixel Vernier time-to-digital converter (TDC) has been implemented, which utilizes two ring oscillators per pixel. Overall chip architecture is introduced as well as pixel architecture and selected simulation results. The pixel consists of a recording channel and TDC part. The recording channel is composed of an inverter-based front-end amplifier with Zimmerman feedback, a discriminator, a calibration block and a threshold setting block. TDC part includes two ring oscillators together with their calibration blocks and additional logic with counters/shift registers that allow for precise ToA measurement (using Vernier method) as well as ToT measurement (using one of the oscillators). Alternatively, single photon counting (SPC) mode can be used. Frequency of oscillators is set in three steps. First, two global 8-bit digital-to-analog converters (DACs) are used for initial setting of all ring oscillators. Then, per-oscillator capacitance bank and 6-bit DAC are used for fine setting. Simulation results of core blocks suggest that the ToA resolution on the order of tens of picoseconds may be achieved. The chips are already fabricated and are currently being prepared for measurements.