A Bootstrap Structure Directly Charged by BUS Voltage with Threshold-Based Digital Control for High-Speed Buck Converter

This article proposes a high-frequency, area-efficient high-side bootstrap circuit with threshold-based digital control (TBDC) that is directly charged by BUS voltage (DCBV). In the circuit, the voltage of the bootstrap is directly obtained from the BUS voltage instead of the on-chip low dropout regulator (LDO), which is more suitable for a high operating frequency. An area-efficient threshold-based digital control structure is used to detect the bootstrap voltage, thereby effectively preventing bootstrap under-voltage or over-voltage that may result in insufficient driving capability, increased loss, or breakdown of the power device. The design and implementation of the circuit are based on CSMC 0.25 µm 60 V BCD technology, with an overall chip area of 1.4 × 1.3 mm2, of which the bootstrap area is 0.149 mm2 and the figure-of-merit (FOM) is 0.074. The experimental results suggest that the bootstrap circuit can normally operate at 5 MHz with a maximum buck converter efficiency of 83.6%. This work plays a vital role in promoting the development of a wide range of new products and new technologies, such as integrated power supplies, new energy vehicles, and data storage centers.

Area-Efficient Universal Code Generator for GPS L1C and BDS B1C Signals

Recently, multi-frequency multi-constellation receivers have been actively studied, which are single receivers that process multiple global navigation satellite system (GNSS) signals for high accuracy and reliability. However, in order for a single receiver to process multiple GNSS signals, it requires as many code generators as the number of supported GNSS signals, and this is one of the problems that must be solved in implementing an efficient multi-frequency multi-constellation receiver. This paper proposes an area-efficient universal code generator that can support both GPS L1C signals and BDS B1C signals. The proposed architecture alleviates the area problem by sharing common hardware in a time-multiplex mode without degrading the overall system performance. According to the result of the synthesis using the CMOS 65 nm process, the proposed universal code generator has an area reduced by 98%, 93%, and 60% compared to the previous memory-based universal code generator (MB UCG), the Legendre-generation universal code generator (LG UCG), and the Weil-generation universal code generator (WG UCG), respectively. Furthermore, the proposed generator is applicable to all Legendre sequence-based codes.

Design of High Speed and Area Efficient Finite Field Multiplier Using Factoring Technique for Communication

In this paper, design of high speed and area efficient finite field multiplier using factoring technique for communication is implemented. Data security plays very important role in present generation. Therefore, initially inputs and key are given to S-Box. The main intent of S-Box is to substitute the input data and key. After that input data and key are merged using S-Box merge. This data will be multiplied using finite field multiplier and to improve the performance along with that mix column technique is applied. Factoring technique will increase the speed of operation. After the data performs shift row operation. At last rounding is performed to the obtained data. At last simulation results shows that effective outcome in terms of delay, memory and security.