path delay
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2022 ◽  
Vol 27 (3) ◽  
pp. 1-31
Author(s):  
Yukui Luo ◽  
Shijin Duan ◽  
Xiaolin Xu

With the emerging cloud-computing development, FPGAs are being integrated with cloud servers for higher performance. Recently, it has been explored to enable multiple users to share the hardware resources of a remote FPGA, i.e., to execute their own applications simultaneously. Although being a promising technique, multi-tenant FPGA unfortunately brings its unique security concerns. It has been demonstrated that the capacitive crosstalk between FPGA long-wires can be a side-channel to extract secret information, giving adversaries the opportunity to implement crosstalk-based side-channel attacks. Moreover, recent work reveals that medium-wires and multiplexers in configurable logic block (CLB) are also vulnerable to crosstalk-based information leakage. In this work, we propose FPGAPRO: a defense framework leveraging P lacement, R outing, and O bfuscation to mitigate the secret leakage on FPGA components, including long-wires, medium-wires, and logic elements in CLB. As a user-friendly defense strategy, FPGAPRO focuses on protecting the security-sensitive instances meanwhile considering critical path delay for performance maintenance. As the proof-of-concept, the experimental result demonstrates that FPGAPRO can effectively reduce the crosstalk-caused side-channel leakage by 138 times. Besides, the performance analysis shows that this strategy prevents the maximum frequency from timing violation.


2022 ◽  
Vol 12 (2) ◽  
pp. 718
Author(s):  
Jiajia Yuan ◽  
Wei Fan ◽  
He Cheng ◽  
Dajie Huang ◽  
Tongyao Du

In this paper, we propose a fast interference spectral imaging system based on liquid crystal (LC) relaxation. The path delay of nematic LC during falling relaxation is used for the scanning of the optical path. Hyperspectral data can be obtained by Fourier transforming the data according to the path delay. The system can obtain two-dimensional spatial images of arbitrary wavelengths in the range of 300–1100 nm with a spectral resolution of 262 cm−1. Compared with conventional Fourier transform spectroscopy, the system can easily collect and integrate all valid information within 20 s. Based on the LC, controlling the optical path difference between two orthogonally polarized beams can avoid mechanical movement. Finally, the potential for application in contactless and rapid non-destructive optical component defect inspection is demonstrated.


Author(s):  
Arun Kumar. Ch

Abstract: The new challenges introduced in the wireless communication systems by the rapid developments of high-speed trains (HSTs) and more usage of the smartphones. The smart transportation involves the large crowd with smart phones, that requires a more efficient network for communication without disconnection. To achieve that, the handover process, need to be done quickly with respect to the speed of the train. To sustain its session connectivity to the internet, it requires the disconnection from the current access point (APc) to the next access point (APn). IN this project, we use the open flow and open stack protocols for integrating the interface between the infrastructure and the controller. Along with this, the integration of software-defined networking and network function virtualization is also done. The project majorly concentrated on the modification of the routes of the packet flow from one access point to the next required access point with the use of the triggering signal from the train which gives the location of the train. The suggested method works by the transmitting the signal from train to the next access point in advance so that the SDN controller changes the path of the packets to the next access point. The parameters like Signal strength, packet loss, average delay, path delay is evaluated. Along with these parameters the energy dissipation near the network also evaluated. The experimental results are evaluated using MATLAB tool. Keywords: Network Function Virtualization, OpenFlow in SDN, OpenStack, Software Defined Network.


2021 ◽  
Author(s):  
Binghao Yan ◽  
Qinrang Liu ◽  
Jianliang Shen ◽  
Liang Dong

2021 ◽  
Author(s):  
S. Sudhakar ◽  
A. Akashwar ◽  
M. Ajay Someshwar ◽  
T. Dhaneshguru ◽  
M. Prem Kumar

The growing network traffic rate in wireless communication demands extended network capacity. Current crypto core methodologies are already reaching the maximum achievable network capacity limits. The combination of AES with other crypto cores and inventing new optimization models have emerged. In this paper, some of the prominent issues related to the existing AES core system, namely, lack of data rate, design complexity, reliability, and discriminative properties. In addition to that, this work also proposes a biometric key generation for AES core that constitutes simpler arithmetic such as substitution, modulo operation, and cyclic shifting for diffusion and confusion metrics which explore cipher transformation level. It is proved that in AES as compared to all other functions S-Box component directly influences the overall system performance both in terms of power consumption overhead, security measures, and path delay, etc.


2021 ◽  
Author(s):  
S. Sivasaravanababu ◽  
T.R. Dineshkumar ◽  
G. Saravana Kumar

The Multiply-Accumulate Unit (MAC) is the core computational block in many DSP and wireless application but comes with more complicated architectures. Moreover the MAC block also decides the energy consumption and the performance of the overall design; due to its lies in the maximal path delay critical propagation. Developing high performance and energy optimized MAC core is essential to optimized DSP core. In this work, a high speed and low power signed booth radix enabled MAC Unit is proposed with highly configurable assertion driven modified booth algorithm (AD-MBE). The proposed booth core is based on core optimized booth radix-4 with hierarchical partial product accumulation design and associated path delay optimization and computational complexity reduction. Here all booth generated partial products are added as post summation adder network which consists of carry select adder (CSA) & carry look ahead (CLA) sequentially which narrow down the energy and computational complexity. Here increasing the operating frequency is achieved by accumulating encoding bits of each of the input operand into assertion unit before generating end results instead of going through the entire partial product accumulation. The FPGA implementation of the proposed signed asserted booth radix-4 based MAC shows significant complexity reduction with improved system performance as compared to the conventional booth unit and conventional array multiplier.


2021 ◽  
Author(s):  
Yueduo Liu ◽  
Zihao Zhu ◽  
Rongxin Bao ◽  
Shiheng Yang ◽  
Jiaxin Liu ◽  
...  
Keyword(s):  

2021 ◽  
Author(s):  
◽  
Caleb Gordon

<p>In measurement and control systems there is often a need to synchronise distributed clocks. Traditionally, synchronisation has been achieved using a dedicated medium to convey time information, typically using the IRIG-B serial protocol. The precision time protocol (IEEE 1588) has been designed as an improvement to current methods of synchronisation within a distributed network of devices. IEEE 1588 is a message based protocol that can be implemented across packet based networks including, but not limited to, Ethernet. Standard Ethernet switches introduce a variable delay to packets that inhibits path delay measurements. Transparent switches have been introduced to measure and adjust for packet delay, thus removing the negative effects that these variations cause.  This thesis describes the hardware and firmware design of an IEEE 1588 transparent end-to-end Ethernet switch for Tekron International Ltd based in Lower Hutt, New Zealand. This switch has the ability to monitor all Ethernet traffic, identify IEEE 1588 timing packets, measure the delay that these packets experience while passing through the switch, and account for this delay by adjusting a time-interval field of the packet as it is leaving the switch. This process takes place at the operational speed of the port, and without introducing significant delay. Time-interval measurements can be made using a high-precision timestamp unit with a resolution of 1 ns. The total jitter introduced by this measurement process is just 4.5 ns through a single switch.</p>


2021 ◽  
Author(s):  
◽  
Caleb Gordon

<p>In measurement and control systems there is often a need to synchronise distributed clocks. Traditionally, synchronisation has been achieved using a dedicated medium to convey time information, typically using the IRIG-B serial protocol. The precision time protocol (IEEE 1588) has been designed as an improvement to current methods of synchronisation within a distributed network of devices. IEEE 1588 is a message based protocol that can be implemented across packet based networks including, but not limited to, Ethernet. Standard Ethernet switches introduce a variable delay to packets that inhibits path delay measurements. Transparent switches have been introduced to measure and adjust for packet delay, thus removing the negative effects that these variations cause.  This thesis describes the hardware and firmware design of an IEEE 1588 transparent end-to-end Ethernet switch for Tekron International Ltd based in Lower Hutt, New Zealand. This switch has the ability to monitor all Ethernet traffic, identify IEEE 1588 timing packets, measure the delay that these packets experience while passing through the switch, and account for this delay by adjusting a time-interval field of the packet as it is leaving the switch. This process takes place at the operational speed of the port, and without introducing significant delay. Time-interval measurements can be made using a high-precision timestamp unit with a resolution of 1 ns. The total jitter introduced by this measurement process is just 4.5 ns through a single switch.</p>


2021 ◽  
Vol 13 (22) ◽  
pp. 4553
Author(s):  
Yunqiao He ◽  
Tianhe Xu ◽  
Fan Gao ◽  
Nazi Wang ◽  
Xinyue Meng ◽  
...  

Coastal Global Navigation Satellite System Reflectometry (GNSS-R) can be used as a valuable supplement for conventional tide gauges, which can be applied for marine environment monitoring and disaster warning. Incidentally, an important problem in dual-antenna GNSS-R altimetry is the crosstalk effect, which means that the direct signal leaks into the down-looking antenna dedicated to the reflected signals. When the path delay between the direct and reflected signals is less than one chip length, the delay waveform of the reflected signal is distorted, and the code-level altimetry precision decreases consequently. To solve this problem, the author deduced the influence of signal crosstalk on the reflected signal structure as the same as the multipath effect. Then, a simulation and a coastal experiment are performed to analyze the crosstalk effect on code delay measurements. The L5 signal transmitted by the Quasi-Zenith Satellite System (QZSS) from a geosynchronous equatorial orbit (GEO) satellite is used to avoid the signal power variations with the elevation, so that high-precision GNSS-R code altimetry measurements are achieved in the experiment. Theoretically and experimentally, we found there exists a bias in proportion to the power of the crosstalk signals and a high-frequency term related to the phase delay between the direct and reflected signals. After weakening the crosstalk by correcting the delay waveform, the results show that the RMSE between 23-h sea level height (SSH) measurements and the in-situ observations is about 9.5 cm.


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