packet classification
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Electronics ◽  
2022 ◽  
Vol 11 (2) ◽  
pp. 199
Author(s):  
Yifei Li ◽  
Jinlin Wang ◽  
Xiao Chen ◽  
Jinghong Wu

Software Defined Network (SDN) currently is widely used in the implementation of new network technologies owing to its distinctive advantages. In changeable SDN environments, the update performance of SDN switches has significant importance for the overall network performance because packet processing could be interrupted by ruleset updating in SDN switches. In order to guarantee high update performance, we propose a new classification algorithm, SplitTrie, based on trie structures and trie splitting. SplitTrie splits rulesets according to the field type vectors of rules. The splitting can improve the update performance because it reduces the trie structure sizes. Experimental results demonstrated that SplitTrie could achieve 20 times of update speed in the complex rulesets comparing the method without trie splitting.


2021 ◽  
Author(s):  
Takashi Fuchino ◽  
Takashi Harada ◽  
Ken Tanaka

Author(s):  
Anita P. ◽  
Manju Devi

The packet classification plays a significant role in many network systems, which requires the incoming packets to be categorized into different flows and must take specific actions as per functional and application requirements. The network system speed is continuously increasing, so the demand for the packet classifier also increased. Also, the packet classifier's complexity is increased further due to multiple fields should match against a large number of rules. In this manuscript, an efficient and high performance modified bitvector (MBV) based packet classification (PC) is designed and implemented on low-cost Artix-7 FPGA. The proposed MBV based PC employs pipelined architecture, which offers low latency and high throughput for PC. The MBV based PC utilizes <2% slices, operating at 493.102 MHz, and consumes 0.1 W total power on Artix-7 FPGA. The proposed PC considers only 4 clock cycles to classify the incoming packets and provides 74.95 Gbps throughput. The comparative results in terms of hardware utilization and performance efficiency of proposed work with existing similar PC approaches are analyzed with better constraints improvement.


2021 ◽  
Vol 11 (18) ◽  
pp. 8693
Author(s):  
Yifei Li ◽  
Jinlin Wang ◽  
Xiao Chen ◽  
Jinghong Wu

With the development of SDN, packet classifiers nowadays need to be provided with low update latency besides fast lookup performance because switches need to respond to update control messages from controllers in time to guarantee real-time service in SDN implementations. Classification in this scenario is called online packet classification. In this paper, we put forward an improved trie-based algorithm for online packet classification (ITOC), in which we provide a trie selection strategy to avoid occasional high update latency in the update process of online trie-based algorithms. Experiments are conducted to validate the effectiveness of our optimization and compare the performance of ITOC with the offline methods, DPDK ACL. Experimental results demonstrate that ITOC has the same level of lookup speed with DPDK ACL and greatly decreased the update latency as well. The update latency of ITOC is only 6.85% of DPDK ACL library in the best case.


2021 ◽  
Author(s):  
Pavel Chuprikov ◽  
Vitalii Demianiuk ◽  
Sergey Gorinsky

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