systems on chip
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2021 ◽  
Author(s):  
Santosh Shetty ◽  
Benjamin Camon Schafer

2021 ◽  
Vol 16 (12) ◽  
pp. 46-51
Author(s):  
Stephan Bäro ◽  
Andreas König
Keyword(s):  
Ip Cores ◽  

2021 ◽  
Vol 15 ◽  
pp. 78-83
Author(s):  
Fateh Boutekkouk

Intellectual Properties reuse has gained widespread acceptance in System-On-Chip design to manage the complexity and shorten the time-to-market. However the need for a standard representation that permits IPs classification, characterization, and integration is still a big challenge. To address this problem, we propose to develop an IPs reuse specific ontology that facilitates IPs reuse at many levels of abstraction and independently from any design language or tool. Our ontology is built using the Protégé-OWL tool


2021 ◽  
Author(s):  
Marcello Cinque ◽  
Gianmaria De Tommasi ◽  
Sara Dubbioso ◽  
Daniele Ottaviano

2021 ◽  
Author(s):  
Subashree Raja ◽  
Padmaja Bhamidipati ◽  
Xiaobang Liu ◽  
Ranga Vemuri
Keyword(s):  

2021 ◽  
Vol 38 (1-2) ◽  
pp. 1-16
Author(s):  
Marcelo Ruaro ◽  
Anderson Sant’ana ◽  
Axel Jantsch ◽  
Fernando Gehm Moraes

Many-Core Systems-on-Chip increasingly require Dynamic Multi-objective Management (DMOM) of resources. DMOM uses different management components for objectives and resources to implement comprehensive and self-adaptive system resource management. DMOMs are challenging because they require a scalable and well-organized framework to make each component modular, allowing it to be instantiated or redesigned with a limited impact on other components. This work evaluates two state-of-the-art distributed management paradigms and, motivated by their drawbacks, proposes a new one called Management Application (MA) , along with a DMOM framework based on MA. MA is a distributed application, specific for management, where each task implements a management role. This paradigm favors scalability and modularity because the management design assumes different and parallel modules, decoupled from the OS. An experiment with a task mapping case study shows that MA reduces the overhead of management resources (-61.5%), latency (-66%), and communication volume (-96%) compared to state-of-the-art per-application management. Compared to cluster-based management (CBM) implemented directly as part of the OS, MA is similar in resources and communication volume, increasing only the mapping latency (+16%). Results targeting a complete DMOM control loop addressing up to three different objectives show the scalability regarding system size and adaptation frequency compared to CBM, presenting an overall management latency reduction of 17.2% and an overall monitoring messages’ latency reduction of 90.2%.


2021 ◽  
Vol 26 (6) ◽  
pp. 1-25
Author(s):  
Dennis R. E. Gnad ◽  
Cong Dang Khoa Nguyen ◽  
Syed Hashim Gillani ◽  
Mehdi B. Tahoori

Field Programmable Gate Arrays ( FPGAs ) are increasingly used in cloud applications and being integrated into Systems-on-Chip. For these systems, various side-channel attacks on cryptographic implementations have been reported, motivating one to apply proper countermeasures. Beyond cryptographic implementations, maliciously introduced covert channel receivers and transmitters can allow one to exfiltrate other secret information from the FPGA. In this article, we present a fast covert channel on FPGAs, which exploits the on-chip power distribution network. This can be achieved without any logical connection between the transmitter and receiver blocks. Compared to a recently published covert channel with an estimated 4.8 Mbit/s transmission speed, we show 8 Mbit/s transmission and reduced errors from around 3% to less than 0.003%. Furthermore, we demonstrate proper transmissions of word-size messages and test the channel in the presence of noise generated from other residing tenants’ modules in the FPGA. When we place and operate other co-tenant modules that require 85% of the total FPGA area, the error rate increases to 0.02%, depending on the platform and setup. This error rate is still reasonably low for a covert channel. Overall, the transmitter and receiver work with less than 3–5% FPGA LUT resources together. We also show the feasibility of other types of covert channel transmitters, in the form of synchronous circuits within the FPGA.


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