Efficient techniques of fractional-N PLL for pervasive wireless applications

Purpose The purpose of this paper to ensure the rapid developments in the radio frequency wireless technology, the synthesis of frequencies for pervasive wireless applications is crucial by implementing the design of low voltage and low power Fractional-N phase locked loop (PLL) for controlling medical devices to monitor remotely patients. Design/methodology/approach The developments urge a technique reliable to phase noise in designing fractional-N PLL with a new eight transistor phase frequency detector and a good linearized charge pump (CP) for speed of operation with minimum mismatches. Findings In applications for portable wireless devices, by proposing a new phase-frequency detector with the removal of dead, blind zones and a modified CP to minimize the mismatch of currents. Originality/value The results are simulated in 45 nm complementary metal oxide semiconductor generic process design kit (GPDK) technology in cadence virtuoso. The phase noise of the proposed Fractiona-N phase locked loop has–93.18, –101.4 and –117 dBc/Hz at 10 kHz, 100 kHz and 1 MHz frequency offsets, respectively, and consumes 3.3 mW from a 0.45 V supply.

Design of Power Efficient Phase Frequency Detector and Voltage Controlled Oscillator for PLL Applications in 45 nm CMOS Technology

A novel phase frequency detector is designed which is made up of 16 transistors whereas conventional is of 48 transistors. This paper also presented the design of charge pump circuit and current starved VCO (CSVCO). These are the critical blocks that are widely used for applications like clock and data recovery circuit, PLL, frequency synthesizer. The proposed PFD eliminates the reset circuit using pass transistor logic and operates effectively at higher frequencies. The circuits are designed using Cadence Virtuoso v6.1 in 45nm CMOS technology having supply voltage 1V. It was found that the power consumption of PFD is 138.2 nW which is significantly lesser than other designs. CSVCO also analysed at operating frequency of 10 MHz to give output oscillation frequency of 1.119 GHz with power dissipation of 18.91 μW. Corner analysis done for both the PFD and CSVCO for various process variations. Monte Carlo analysis also done for the proposed PFD and presented CSVCO to test the circuit reliableness.

Integer N Synthesizer Design for LoRa Transceivers

This paper presents the study and design of an Integer N synthesizer model for three LoRa ISM bands: 430 MHz 868 MHz and 915 MHz. The proposed topology is composed by two voltage controlled oscillators working in two different bands. The presented model uses the same phase-frequency detector, charge pump and loop filter. This study is focused on dynamic and steady-state analysis in order to infer the synthesizer stability and bandwidth. The performed study shows that the settling time for all bands is less than 40 µs for a bandwidth of 102 kHz.

An integer-N frequency synthesizer for medical implantable devices

This thesis proposes an Integer-N frequency synthesizer in TSMC 0.18µm technology. The design is aimed for MICS (Medical Implantable Communication Services) devices operating at 402-406 MHz. A low phase noise, wide frequency range Quadrature Voltage Controlled Oscillator (QVCO) has been designed and simulated. The simulated phase noise @ 160 KHz offset is -100.3 dBc/Hz with the power consumption of 0.9 mW. This design addresses the small size, low phase noise and low power requirements for the Implantable devices. A wide frequency range Source Coupled Logic (SCL)32/33 prescaler divider has been designed. The program counter and Swallow counter have been implemented in Verilog-A which allow a division ratio of 2690 from the output of the QVCO. A phase frequency detector based on a modified TSPC D-Flip Flop is designed, which leads to a faster response time. The phase frequency detector, the charge pump, and the loop filter would consume 0.5 mW power. The total power consumption of the synthesizer is at 4.6 mW with 2% steady state settlement time of 160 μs.

An integer-N frequency synthesizer for medical implantable devices

This thesis proposes an Integer-N frequency synthesizer in TSMC 0.18µm technology. The design is aimed for MICS (Medical Implantable Communication Services) devices operating at 402-406 MHz. A low phase noise, wide frequency range Quadrature Voltage Controlled Oscillator (QVCO) has been designed and simulated. The simulated phase noise @ 160 KHz offset is -100.3 dBc/Hz with the power consumption of 0.9 mW. This design addresses the small size, low phase noise and low power requirements for the Implantable devices. A wide frequency range Source Coupled Logic (SCL)32/33 prescaler divider has been designed. The program counter and Swallow counter have been implemented in Verilog-A which allow a division ratio of 2690 from the output of the QVCO. A phase frequency detector based on a modified TSPC D-Flip Flop is designed, which leads to a faster response time. The phase frequency detector, the charge pump, and the loop filter would consume 0.5 mW power. The total power consumption of the synthesizer is at 4.6 mW with 2% steady state settlement time of 160 μs.