A Quality-assured Approximate Hardware Accelerators–based on Machine Learning and Dynamic Partial Reconfiguration

Machine learning is widely used these days to extract meaningful information out of the Zettabytes of sensors data collected daily. All applications require analyzing and understanding the data to identify trends, e.g., surveillance, exhibit some error tolerance. Approximate computing has emerged as an energy-efficient design paradigm aiming to take advantage of the intrinsic error resilience in a wide set of error-tolerant applications. Thus, inexact results could reduce power consumption, delay, area, and execution time. To increase the energy-efficiency of machine learning on FPGA, we consider approximation at the hardware level, e.g., approximate multipliers. However, errors in approximate computing heavily depend on the application, the applied inputs, and user preferences. However, dynamic partial reconfiguration has been introduced, as a key differentiating capability in recent FPGAs, to significantly reduce design area, power consumption, and reconfiguration time by adaptively changing a selective part of the FPGA design without interrupting the remaining system. Thus, integrating “Dynamic Partial Reconfiguration” (DPR) with “Approximate Computing” (AC) will significantly ameliorate the efficiency of FPGA-based design approximation. In this article, we propose hardware-efficient quality-controlled approximate accelerators, which are suitable to be implemented in FPGA-based machine learning algorithms as well as any error-resilient applications. Experimental results using three case studies of image blending, audio blending, and image filtering applications demonstrate that the proposed adaptive approximate accelerator satisfies the required quality with an accuracy of 81.82%, 80.4%, and 89.4%, respectively. On average, the partial bitstream was found to be 28.6 smaller than the full bitstream .

Evolvable Hardware-Based Data Security System Using Image Steganography Through Dynamic Partial Reconfiguration

A highly secure communication method is essential for end users for the exchange of information which is not interpreted by an intruder. Cryptography plays a crucial role in the current and upcoming digital worlds, for secure data transmission in wired and wireless networks. Asymmetric and symmetric cryptographic algorithms encrypt data against vulnerable attacks and transfer to authenticated users. Steganography is a method for providing secure information with the help of a carrier file (text, video, audio, image, etc.). This paper proposes Deoxyribonucleic Acid (DNA)-based asymmetric algorithm which is used to encrypt the patient’s secret information and its performance is compared with ElGamal, RSA and Diffie–Hellman (DH) cryptographic algorithms. The proposed asymmetric algorithm is applied to image steganography which is used for encrypting and concealing the patient’s secret information in a cover image. The proposed method consumes less hardware resources with improved latency. Dynamic Partial Reconfiguration (DPR) allows to transform a selective area rather than complete shutdown of the entire system during bitstream configuration. Cryptosystem with DPR is designed, synthesized in Xilinx Vivado and simulated in Vivado simulator. The design is targeted at Basys3, Nexys4 DDR and Zync-7000 all-programmable SOC (AP SoC) architectures and programmed with secure partial bit files to avoid vulnerable attacks in the channel.

An FPGA-based network system with service-uninterrupted remote functional update

The recent emergence of 5G network enables mass wireless sensors deployment for internet-of-things (IoT) applications. In many cases, IoT sensors in monitoring and data collection applications are required to operate continuously and active at all time (24/7) to ensure all data are sampled without loss. Field-programmable gate array (FPGA)-based systems exhibit a balanced processing throughput and datapath flexibility. Specifically, datapath flexibility is acquired from the FPGA-based system architecture that supports dynamic partial reconfiguration feature. However, device functional update can cause interruption to the application servicing, especially in an FPGA-based system. This paper presents a standalone FPGA-based system architecture that allows remote functional update without causing service interruption by adopting a redundancy mechanism in the application datapath. By utilizing dynamic partial reconfiguration, only the updating datapath is temporarily inactive while the rest of the circuitry, including the redundant datapath, remain active. Hence, there is no service interruption and downtime when a remote functional update takes place due to the existence of redundant application datapath, which is critical for network and communication systems. The proposed architecture has a significant impact for application in FPGA-based systems that have little or no tolerance in service interruption.

FPGA-based switch-level fault emulation using modular-based dynamic partial reconfiguration

Fault simulation is a process of purposely injecting faults into a target circuit and observing a circuit's behavior in the presence of faulty logic. This observation helps designers to implement certain fault tolerance schemes thereby combating hardware failures. Fault simulation in most implementations has until now been software-based. Several fault emulation approaches have been proposed to accelerate fault simulation process using FPGA. There are generally two types of hardware fault injection: injector-based and reconfiguration-based. Injector-based methods require inserting fault injector circuitry into the circuit under test thus adding hardware overhead. On the other hand, reconfigurable-based methods require much less hardware overhead. However, these methods may be very slow because reconfiguring an entire FPGA device can take several seconds. This long confirmation time is usually the bottleneck of the emulation system. This project proposes a novel switch-level fault emulation system utilizing FPGA modular-based dynamic partial reconfiguration (DPR). In the proposed approach, faults are modeled at switch-level for an accurate fault list and mapped to gate-level for efficient synthesis. In addition, circuit-under-test is partitioned using an unbalanced tree structure to facilitate modular-based DPR. Modular-based DPR partitions a design into modules, and each module can be reconfigured independently without shutting down the FPGA. This capability is applied to fault injection where each circuit partition can be reconfigured individually without erasing the rest of FPGA. First a partial configuration bitstream representing the faulty partition is created. Fault injection can then be performed by downloading only this partial bitstream to FPGA, thereby eliminating the need for full-device reconfiguration and therefore reducing fault emulation runtime. This report presents both a theoretical explanation and the implementation details regarding this approach. Experimental results are also be provided. [sic]

FPGA-based switch-level fault emulation using modular-based dynamic partial reconfiguration

Fault simulation is a process of purposely injecting faults into a target circuit and observing a circuit's behavior in the presence of faulty logic. This observation helps designers to implement certain fault tolerance schemes thereby combating hardware failures. Fault simulation in most implementations has until now been software-based. Several fault emulation approaches have been proposed to accelerate fault simulation process using FPGA. There are generally two types of hardware fault injection: injector-based and reconfiguration-based. Injector-based methods require inserting fault injector circuitry into the circuit under test thus adding hardware overhead. On the other hand, reconfigurable-based methods require much less hardware overhead. However, these methods may be very slow because reconfiguring an entire FPGA device can take several seconds. This long confirmation time is usually the bottleneck of the emulation system. This project proposes a novel switch-level fault emulation system utilizing FPGA modular-based dynamic partial reconfiguration (DPR). In the proposed approach, faults are modeled at switch-level for an accurate fault list and mapped to gate-level for efficient synthesis. In addition, circuit-under-test is partitioned using an unbalanced tree structure to facilitate modular-based DPR. Modular-based DPR partitions a design into modules, and each module can be reconfigured independently without shutting down the FPGA. This capability is applied to fault injection where each circuit partition can be reconfigured individually without erasing the rest of FPGA. First a partial configuration bitstream representing the faulty partition is created. Fault injection can then be performed by downloading only this partial bitstream to FPGA, thereby eliminating the need for full-device reconfiguration and therefore reducing fault emulation runtime. This report presents both a theoretical explanation and the implementation details regarding this approach. Experimental results are also be provided. [sic]