Implementation of Data Security with Wallace Tree Approach Using Elliptical Curve Cryptography on FPGA

The growth of computing resources and parallel computing has led to significant needs for efficient cryptosystems over the last decade. Elliptic Curve Cryptography (ECC) provides faster computation over other asymmetric cryptosystems such as RSA and greater security. For many cryptography operations, ECC can be used: hidden key exchange, message encryption, and digital signature. There is thus a trade-off between safety and efficiency with regard to speed, area and power requirements. This paper provides a good ECC approach to encryption by replacing the Vedic multiplier (16 bit) with the Wallace tree multiplier with an improved output (128 bit). The proposed design processes data recurringly with less volume, less power consumption and greater velocity, in addition to improving efficiency. Using Xilinx 2015.2 software, the entire proposed design is synthesized and simulated and implemented on the ZYNQ FPGA Board. Compared with previous implementations, a significant improvement in field efficiency, time complexity and energy demand is demonstrated by the proposed design.

A Fresh Design of Power Effective Adapted Vedic Multiplier for Modern Digital Signal Processors

The Multiply Accumulate (MAC) unit constructed using antiquated Vedic mathematical practice and the efficiency of the vertical and transversely of Vedic approach for multiplication, which gives a distinction in genuine cycle of Multiplier itself. Vedic-Mathematics is depend on 16-Sutras, in that Urdhva-Triyakbhyam (UT) more productive one. It literally means vertical and cross wise operations. It eliminates unwanted multiplication and allows the parallel creation of partial products and addition steps. The adders are utilized to append the partial-product generated in the Vedic mathematics methodology to drops the combinational lag. MAC is an essential unit in the digital signal processors, to show the characters like speed, power as well as area. Hence, finer multiplier plans are to increase the order of the system. The Modified sum product algorithm based Vedic multiplier is one such promising solution. It has a rapid multiplication process and reaches a less calculation complexity above its traditional multiplier. Array multiplier, Baugh-Wooley multiplier, Wallace-tree multiplier and Vedic multiplier were created in the existing work. In proposed work Vedic multiplier, using modified sum product algorithm was designed. The structure design coded in verilog and parameter analysis was done in Xilinx. The parameters like delay as well as power were compare between existing and proposed. When comparing with different multiplier with our proposed work delay get reduced. Comparing with existing multiplier the proposed 4x4 Vedic multiplier have 49.12% reduction in delay. Comparing with existing multiplier the proposed Vedic 4x4 multiplier have 42.51% reduction in power.

VLSI implementation of Wallace Tree Multiplier using Ladner-Fischer Adder

Nowadays, most of the application depends on arithmetic designs such as an adder, multiplier, divider, etc. Among that, multipliers are very essential for designing industrial applications such as Finite Impulse Response, Fast Fourier Transform, Discrete cosine transform, etc. In the conventional methods, different kind of multipliers such as array multiplier, booth multiplier, bough Wooley multiplier, etc. are used. These existing multipliers are occupied more area to operate. In this study, Wallace Tree Multiplier (WTM) is implemented to overcome this problem. Two kinds of multipliers have designed in this research work for comparison. At first, existing WTM is designed with normal full adders and half adders. Next, proposed WTM is designed using Ladner Fischer Adder (LFA) to improve the hardware utilization and reduce the power consumption. Field Programmable Gate Array (FPGA) performances such as slice Look Up Table (LUT), Slice Register, Bonded Input-Output Bios (IOB) and power consumption are evaluated. The proposed WTM-LFA architecture occupied 374 slice LUT, 193 slice register, 59 bonded IOB, and 26.31W power. These FPGA performances are improved compared to conventional multipliers such asModified Retiming Serial Multiplier (MRSM), Digit Based Montgomery Multiplier (DBMM), and Fast Parallel Decimal Multiplier (FPDM).

FPGA Implementation of Adaptive Absolute SCORE Algorithm for Cognitive Radio Spectrum Sensing with WTM and LFA

Cognitive Radio (CR) is generally a wireless communication system that has the ability to improve the network’s system-capacity. Since, the white space or temporally unused spectrum are used to enhance the systemcapacity and the important operation involved in the cognition cycle is spectrum sensing. This spectrum sensing supports the Cognitive Radio users to adjust with the environment by identifying the white/vacant spaces without creating any interference to the primary user communication. The traditional filters such as Finite Impulse Response (FIR) filters and median filters used in the spectrum sensing obtains high area utilization in Cognitive Radio. In order to overcome this, an Adaptive Absolute SCORE (AAS) technique is developed based on the FIR for improving the sensing function and radio sensitivity. The area and frequency of the AAS are enhanced by using the Wallace tree multiplier (WTM) and Ladner-Fischer Adder (LFA) in the design of the FIR. The proposed architecture used for the spectrum sensing is named as AAS-WTM-LFA. This AAS-WTM-LFA architecture is developed in the Xilinx tool for different Virtex devices. The performance of AAS-WTM-LFA is analyzed in terms of LUT, slices, flip flops, bonded Input and Output Block (IOB), frequency and power. Additionally, the quality of signal processed through the AAS-WTM-LFA architecture is analyzed as Bit Error Rate (BER) and False Acceptance Rate (FAR). Additionally, the AAS-WTM-LFA architecture is compared with ACS, AAS, AAS-CSLA, AAS-R8-CSA and AASR8-CSLA. The number of LUT for AAS-WTM-LFA architecture is 247 for Spartan 6 device, that is less when compared to the remaining architectures.