pipelined adc
Recently Published Documents


TOTAL DOCUMENTS

597
(FIVE YEARS 68)

H-INDEX

32
(FIVE YEARS 4)

Micromachines ◽  
2022 ◽  
Vol 13 (1) ◽  
pp. 114
Author(s):  
Dongdong Chen ◽  
Xinhui Cui ◽  
Qidong Zhang ◽  
Di Li ◽  
Wenyang Cheng ◽  
...  

As traditional ultrasonic imaging systems (UIS) are expensive, bulky, and power-consuming, miniaturized and portable UIS have been developed and widely utilized in the biomedical field. The performance of integrated circuits (ICs) in portable UIS obviously affects the effectiveness and quality of ultrasonic imaging. In the ICs for UIS, the analog-to-digital converter (ADC) is used to complete the conversion of the analog echo signal received by the analog front end into digital for further processing by a digital signal processing (DSP) or microcontroller unit (MCU). The accuracy and speed of the ADC determine the precision and efficiency of UIS. Therefore, it is necessary to systematically review and summarize the characteristics of different types of ADCs for UIS, which can provide valuable guidance to design and fabricate high-performance ADC for miniaturized high resolution UIS. In this paper, the architecture and performance of ADC for UIS, including successive approximation register (SAR) ADC, sigma-delta (Σ-∆) ADC, pipelined ADC, and hybrid ADC, have been systematically introduced. In addition, comparisons and discussions of different types of ADCs are presented. Finally, this paper is summarized, and presents the challenges and prospects of ADC ICs for miniaturized high resolution UIS.


2021 ◽  
Author(s):  
Senji Liu ◽  
Xinpeng Xing ◽  
Lei Qian

2021 ◽  
Author(s):  
Weiqi Gu ◽  
Peng Miao ◽  
Fei Li ◽  
Huan Wang ◽  
Bowen Ding
Keyword(s):  

Circuit World ◽  
2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
D.S. Shylu Sam ◽  
P. Sam Paul

Purpose In parallel sampling method, the size of the sampling capacitor is reduced to improve the bandwidth of the ADC. Design/methodology/approach Various low-power techniques for 10-bit 200MS/s pipelined analog-to-digital converter (ADC) are presented. This work comprises two techniques including parallel sampling and switched op-amp sharing technique. Findings This paper aims to study the effect of parallel sampling and switched op-amp sharing techniques on power consumption in pipelined ADC. In switched op-amp sharing technique, the numbers of op-amps used in the stages are reduced. Because of the reduction in the size of capacitors in parallel sampling technique and op-amps in the switched op-amp sharing technique, the power consumption of the proposed pipelined ADC is reduced to a greater extent. Originality/value Simulated the 10-bit 200MS/s pipelined ADC with complementary metal oxide semiconductor process and the simulation results shows a maximum differential non-linearity of +0.31/−0.31 LSB and the maximum integral non-linearity (of +0.74/−0.74 LSB with 62.9 dB SFDR, 55.90 dB SNDR and ENOB of 8.99 bits, respectively, for 18mW power consumption with the supply voltage of 1.8 V.


Author(s):  
Yigi Kwon ◽  
Byounghan Min ◽  
Jinhwan Lee ◽  
Wooyol Lee ◽  
Sunghyun Yang
Keyword(s):  

2021 ◽  
Author(s):  
Shylu Sam ◽  
D. Jackuline Moni ◽  
P.Sam Paul ◽  
D. Nirmal

Abstract This work presents a low power 10-bit 40 MSPS Pipelined ADC with 1.8V supply voltage in a 180nm silicon based CMOS process. Simultaneous capacitor sharing and op-amp sharing technique is used between two successive stages of a Sample-and Hold Ampifier (SHA) to reduce the power consumption.The memory effect in the proposed ADC is eliminated by a low input capacitance variable gm op-amp. The differential and integral nonlinearity of the converter are within LSB.Simulation results show that the required Signal-Furious-Dynamic range (SFDR) of 70dB, Signal-to -Noise-plus Distortion Ratio (SNDR) of 56.1dB and 9.02 Effective Number of Bits ( ENOB ) has been achieved with a 2MHz, 1-Vp−p,diff input signal while consuming only 7.3mW power from 1.8V supply.


Sign in / Sign up

Export Citation Format

Share Document