Design of Hybrid Schottky-Ohmic Gate in Normally-Off p-GaN Gate AlGaN/GaN HEMTs

This study proposes three hybrid Schottky-ohmic gate structures for normally-off p-GaN gate AlGaN/GaN HEMTs. One has a Schottky-gate cover on the ohmic-gate and has part of the area contact to the p-GaN surface at the left and right sides of ohmic-gate (Structure A). The two others only have the Schottky-gate contact to the p-GaN surface at the left side (Structure B) or right side (Structure C) of the ohmic-gate. Different gate metal designs change the hole injection from p-GaN to GaN channel and show various gate leakages. The optimized contact length of Schottky-gate can suppress on-state gate leakage current over two orders of magnitude compared to conventional ohmic p-GaN gate HEMT. The improved on-state maximum drain current is over 60 mA/mm compared to Schottky p-GaN gate HEMT. Optimal performance in Structure B with Schottky-gate contact length ranges from 0.8 to 1.8 μm in a 2 μm gate geometry.

A loadless 4T SRAM powered by gate leakage current with a high tolerance for fluctuations in device parameters

A novel loadless four-transistor static random access memory cell is proposed that consists of two N-type driver MOSFETs and two P-type access ones whose gate leakage currents from word-line are used for holding data in the cell. It is shown that the proposed cell has a higher tolerance for manufacturing device fluctuations compared with the conventional loadless 4T SRAM. Furthermore, it is free from bit-line disturb in contrast to the conventional cell. It is confirmed by simulation in 32nm technology node that the read static noise margin of the proposed cell reaches 138.7% of the six-transistor SRAM cell and that the hold static noise margin can be acceptable when the gate insulator thickness of the P-type access MOSFETs is made thinner than the N-type driver MOSFETs. The retention current for the proposed cell decreases to 66.7% of the 6TSRAM and the data rate in read increases to 125%.

New Submicron Low Gate Leakage In0.52Al0.48As-In0.7Ga0.3As pHEMT for Low-Noise Applications

Conventional pseudomorphic high electron mobility transistor (pHEMTs) with lattice-matched InGaAs/InAlAs/InP structures exhibit high mobility and saturation velocity and are hence attractive for the fabrication of three-terminal low-noise and high-frequency devices, which operate at room temperature. The major drawbacks of conventional pHEMT devices are the very low breakdown voltage (<2 V) and the very high gate leakage current (∼1 mA/mm), which degrade device and performance especially in monolithic microwave integrated circuits low-noise amplifiers (MMIC LNAs). These drawbacks are caused by the impact ionization in the low band gap, i.e., the InxGa(1−x)As (x = 0.53 or 0.7) channel material plus the contribution of other parts of the epitaxial structure. The capability to achieve higher frequency operation is also hindered in conventional InGaAs/InAlAs/InP pHEMTs, due to the standard 1 μm flat gate length technology used. A key challenge in solving these issues is the optimization of the InGaAs/InAlAs epilayer structure through band gap engineering. A related challenge is the fabrication of submicron gate length devices using I-line optical lithography, which is more cost-effective, compared to the use of e-Beam lithography. The main goal for this research involves a radical departure from the conventional InGaAs/InAlAs/InP pHEMT structures by designing new and advanced epilayer structures, which significantly improves the performance of conventional low-noise pHEMT devices and at the same time preserves the radio frequency (RF) characteristics. The optimization of the submicron T-gate length process is performed by introducing a new technique to further scale down the bottom gate opening. The outstanding achievements of the new design approach are 90% less gate current leakage and 70% improvement in breakdown voltage, compared with the conventional design. Furthermore, the submicron T-gate length process also shows an increase of about 58% and 33% in fT and fmax, respectively, compared to the conventional 1 μm gate length process. Consequently, the remarkable performance of this new design structure, together with a submicron gate length facilitatesthe implementation of excellent low-noise applications.