Design and Implementation of Carbon Nano-tube based Full Adder at 32nm Technology for High Speed and Power Efficient Arithmetic Applications

Due to physical, material, technological, power-thermal and economical difficulties, scaling of CMOS transistors will stop very soon. Due to efficiency of power and speed compared to CMOS transistors, Carbon Nano-tube transistors are best suitable element to design logic circuits. So, CNTFETS have been utilized in designing of proposed full adder (FA) and 4-bit ripple carry adder (RCA) in this paper. Proposed FA and RCA have been compared to rival designs on bases of power, speed and power-delay-product (PDP). FA and RCA circuits have been analysed with the variation of temperature from 0°C to 100°C while the variation of supply voltages is from 0.7V to 1.3V. For all temperatures and all supply voltages, proposed FA and proposed RCA have the least power consumption, shortest delay and lowest PDP. SPICE has been utilized for simulating FAs and RCAs in 32 nm process node. Even though the fabrication is complicated than CMOS counterparts but simulation results confirm usefulness of proposed FA and RCA for high speed and power efficient arithmetic applications.

Three-Phase Induction Motors Online Protection against Unbalanced Supply Voltages

Three-phase induction motors (IMs) are the main workhorse in industry due to their many advantages as compared to other types of industrial motors. However, the efficiency and lifetime of IMs can be considerably affected by some operating conditions, in particular those related to unbalanced supply voltages (USV), which is quite a common condition in industrial plants. Therefore, early detection and a precise severity estimation of the USV for all working conditions can prevent major breakdowns and increase reliability and safety of industrial facilities. This paper proposes a reliable method allowing for a precise and online detection of the USV condition, by monitoring a pertinent indicator calculated using the voltage symmetrical components. The effectiveness of the proposed method is validated experimentally for several different working conditions, and a comparison with other indicators available in the literature is also performed.

Operational Amplifier Design Employing DTMOS Technique with Dual Supply Voltages

An operational amplifier (OPAMP) for portable devices with dual supply voltage is presented in this work. The design is realized with a 600[Formula: see text]mV supply for the core design and a 1.8[Formula: see text]V supply for the biasing circuit to improve input common mode range (ICMR), gain, and common mode rejection ratio (CMRR). The designed amplifier is implemented with dynamic threshold voltage MOSFET (DTMOS) transistors to decrease power consumption and increase the performance of the design. The power consumption of the core design is obtained as 2[Formula: see text][Formula: see text]W while the biasing circuitry consumes 7.38[Formula: see text][Formula: see text]W. The application of different supply voltages has greatly increased the gain of the circuit, where the circuit exhibits 100.2[Formula: see text]dB DC gain and 3.41[Formula: see text]MHz gain bandwidth product (GBW). CMRR of the designed circuit is 84.22[Formula: see text]dB. The simulations are performed in Cadence environment with 0.18[Formula: see text][Formula: see text]m CMOS technology.

A Low-Power CMOS Bandgap Voltage Reference for Supply Voltages Down to 0.5 V

A voltage reference is strictly required for sensor interfaces that need to perform nonratiometric data acquisition. In this work, a voltage reference capable of working with supply voltages down to 0.5 V is presented. The voltage reference was based on a classic CMOS bandgap core, properly modified to be compatible with low-threshold or zero-threshold MOSFETs. The advantages of the proposed circuit are illustrated with theoretical analysis and supported by numerical simulations. The core was combined with a recently proposed switched capacitor, inverter-like integrator implementing offset cancellation and low-frequency noise reduction techniques. Experimental results performed on a prototype designed and fabricated using a commercial 0.18 μm CMOS process are presented. The prototype produces a reference voltage of 220 mV with a temperature sensitivity of 45 ppm/°C across a 10–50 °C temperature range. The proposed voltage reference can be used to source currents up to 100 μA with a quiescent current consumption of only 630 nA.

MATRIX16: A 16-Channel Low-Power TDC ASIC with 8 ps Time Resolution

This paper presents a highly configurable 16-channel TDC ASIC designed in a commercial 180 nm technology with the following features: time-of-flight and time-over-threshold measurements, 8.6 ps LSB, 7.7 ps jitter, 5.6 ps linearity error, up to 5 MHz of sustained input rate per channel, 9.1 mW of power consumption per channel, and an area of 4.57 mm2. The main contributions of this work are the novel design of the clock interpolation circuitry based on a resistive interpolation mesh circuit and the capability to operate at different supply voltages and operating frequencies, thus providing a compromise between TDC resolution and power consumption.