Exploiting Data Compression for Adaptive Block Placement in Hybrid Caches

STT-RAM (Spin-Transfer Torque Random Access Memory) appears to be a viable alternative to SRAM-based on-chip caches. Due to its high density and low leakage power, STT-RAM can be used to build massive capacity last-level caches (LLC). Unfortunately, STT-RAM has a much longer write latency and a much greater write energy than SRAM. Researchers developed hybrid caches made up of SRAM and STT-RAM regions to cope with these challenges. In order to store as many write-intensive blocks in the SRAM region as possible in hybrid caches, an intelligent block placement policy is essential. This paper proposes an adaptive block placement framework for hybrid caches that incorporates metadata embedding (ADAM). When a cache block is evicted from the LLC, ADAM embeds metadata (i.e., write intensity) into the block. Metadata embedded in the cache block are then extracted and used to determine the block’s write intensity when it is fetched from main memory. Our research demonstrates that ADAM can enhance performance by 26% (on average) when compared to a baseline block placement scheme.

Reliability Tradeoffs in Design of Volatile and Nonvolatile Caches

Researchers have explored both volatile memories (e.g., SRAM and embedded DRAM) and nonvolatile memories (NVMs, such as resistive RAM) for design of on-chip caches. However, both volatile and nonvolatile memories present unique reliability challenges. NVMs are immune to radiation-induced soft errors, however, due to their limited write endurance, they are vulnerable to hard errors under nonuniform write distribution. By contrast, SRAM has high write endurance but is susceptible to soft errors due to cosmic radiation. SRAM–NVM hybrid caches and the management techniques for them aim to bring the best of SRAM and NVM together, however, the reliability implications of them have not been well understood. In this paper, we show that there are inherent tradeoffs in improving resilience to hard and soft errors in hybrid caches such that mitigating one may result in aggravating another. We confirm this by experiments with two recent hybrid cache management techniques. We also re-examine cache design trends in modern processors from reliability perspective. This paper provides valuable insights to system developers for making reliability-aware design decisions.