Review of Bumpless Build Cube (BBCube) Using Wafer-on-Wafer (WOW) and Chip-on-Wafer (COW) for Tera-Scale Three-Dimensional Integration (3DI)

Bumpless Build Cube (BBCube) using Wafer-on-Wafer (WOW) and Chip-on-Wafer (COW) for Tera-Scale Three-Dimensional Integration (3DI) is discussed. Bumpless interconnects between wafers and between chips and wafers are a second-generation alternative to the use of micro-bumps for WOW and COW technologies. WOW and COW technologies for BBCube can be used for homogeneous and heterogeneous 3DI, respectively. Ultra-thinning of wafers down to 4 μm offers the advantage of a small form factor, not only in terms of the total volume of 3D ICs, but also the aspect ratio of Through-Silicon-Vias (TSVs). Bumpless interconnect technology can increase the number of TSVs per chip due to the finer TSV pitch and the lower impedance of bumpless TSV interconnects. In addition, high-density TSV interconnects with a short length provide the highest thermal dissipation from high-temperature devices such as CPUs and GPUs. This paper describes the process platform for BBCube WOW and COW technologies and BBCube DRAMs with high speed and low IO buffer power by enhancing parallelism and increasing yield by using a vertically replaceable memory block architecture, and also presents a comparison of thermal characteristics in 3D structures constructed with micro-bumps and BBCube.

Failure Localization Techniques for 7nm & 16nm Process Nodes in Monolithic & 2.5D SSIT Package Technology Using OBIRCH, LVP and Advance Die Thinning Method

High performance IC's have driven the semiconductor industry towards the sub-nanometer technology nodes for several years. At 16nm and beyond, the spatial resolution and sensitivity of some diagnostic equipment used for failure analysis have reached certain limitations. The accuracy of isolating a faulty signal in a tightly packed group of transistors in a die becomes more challenging. However, with the improvement of SIL (Solid Immersion Lens) based lens technology with higher N.A. (Numeric Aperture), combined with precision die thinning process, allowed some very promising results. This paper demonstrates successful diagnostic techniques utilizing the SIL lens and a variety of die thinning preparation techniques on 7nm and 16nm process nodes in both monolithic and 2.5D SSIT (Stacked Silicon Interconnect Technology) packages.

Design of Microfabricated Mechanically Interlocking Metamaterials for Reworkable Heterogeneous Integration

Next–generation interconnects utilizing mechanically interlocking structures enable permanent and reworkable joints between microelectronic devices. Mechanical metamaterials, specifically dry adhesives, are an active area of research which allows for the joining of objects without traditional fasteners or adhesives, and in the case of chip integration, without solder. This paper focuses on reworkable joints that enable chips to be removed from their substrates to support reusable device prototyping and packaging, creating the possibility for eventual pick-and-place mechanical bonding of chips with no additional bonding steps required. Analytical models are presented and are verified through Finite Element Analysis (FEA) assuming pure elastic behavior. Sliding contact conditions in FEA simplify consideration of several design variations but contribute ~10% uncertainty relative to experiment, analysis, and point-loaded FEA. Two designs are presented; arrays of flat cantilevers have a bond strength of 6.3 kPa, and non-flat cantilevers have a strength of 29 kPa. Interlocking designs present self-aligning in-plane forces that emerge from translational perturbation from perfect alignment. Stresses exceeding the material yield stress during adhesion operations present a greater concern for repeatable operation of compliant interlocking joints and will require further study quantifying and accommodating plastic deformation. Designs joining a rigid array with a complementary compliant cantilever array preserve the condition of reworkability for the surface presenting the rigid array. Eventual realization of interconnect technology based on this study will provide a great improvement of functionality and adaptability in heterogeneous integration and microdevice packaging.