A Novel Method to Control Leakage and Noise in Domino Circuit for Wide Fan-in OR Logic

This paper proposes a novel method to control leakage and noise in domino circuits for wide fan-in OR logic with low power consumption, low process variation, and higher noise margin under the similar delay condition. In the proposed method, output and dynamic nodes are isolated from the PDN (Pull-Down Network) to improve the noise immunity and reduce switching activity. Further, with the aid of a transistor in the stack, the sub-threshold current is reduced. Thus, the proposed domino is applicable for high-speed and low-power applications in deep sub-micro-range. Simulation results show that the proposed domino improves the noise immunity and figure of merit (FOM) by factors of 1.95 and 2.34, respectively, with respect to the conventional domino with a footer. Along with this improvement, 26% reduction is also observed in power consumption. The entire simulations for all the domino circuits are done at 45-nm CMOS technology by using SPECTRE simulator under the Cadence Virtuoso environment.

Design of CNTFET Based Domino Wide OR Gates Using Dual Chirality for Reducing Subthreshold Leakage Current

The leakage current is prime concern in the modern portable battery operated device. However, various techniques are presented and performance is evaluated using MOSFET and FinFET devices. To further reduce leakage current for improved battery backup in portable devices, new devicesnamely Carbon Nano Tube Field Effect transistors (CNTFETs) can be used for design of different digital circuits. In this paper, subthreshold leakage power of dual chiral CNTFET based domino circuit is investigated and also the results are compared with single chiral CNTFET domino circuits. For better performance, threshold voltage of CNTFET in critical path is varied by changing the diameter or chirality of carbon nanotube. Subthreshold leakage power saving in dual chiral standard and LECTOR based domino circuits for OR2, OR4, OR8 & OR16 for low temperature (25°C) & low input ranges from 90.36- 95.96% and from 91.97-97.3%; for low temperature & high input ranges from 90.66-95.23% and from 92.85-96.39%; for high temperature (110°C) & low input ranges from 89.24- 99.73% and from 27.5-99.83%; for high temperature & high input ranges from 89.65-97.86% and from 91.85-99.76% when compared with single chiral standard and LECTOR based domino circuits respectively.

A New Keeper Domino Logic Based Full Adder for High Speed Arithmetic Circuits

Objective: A new efficient keeper circuit has been proposed in this article for achieving low leakage power consumption and to improve power delay product of the dynamic logic using carbon nanotube MOSFET. Method: As a benchmark, an one-bit adder has been designed and characterized with both technologies Si-MOSFET and CN-MOSFET using proposed and existing dynamic circuits. Furthermore, a comparison has been made to demonstrate the superiority of CN-MOSFET technology with Synopsys HSPICE tool for multiple bit adders available in the literature. Result: The simulation results show that the proposed keeper circuit provides lower static and dynamic power consumption up to 57 and 40% respectively, as compared to the domino circuits using 32nm CN-MOSFET technology provided by Stanford University. Moreover, the proposed keeper configuration provides better performance using SiMOSFET and CN-MOSFET technologies. Conclusion: A comparison of the proposed keeper with previously published designs is also given in terms of power consumption, delay and power delay product with the improvement up to 75, 18 and 50% respectively. The proposed circuit uses only two transistors, so it requires less area and gives high efficiency.

A Novel Approach for Analysis CNTFET Based Domino circuit in Nano-Scale Design

As semiconductor industries is developing day by day to meet the requirement of today’s world. As scaling of ICs day by day to introduce functionality of the device while fabrication more and more component which results in shorter the life of the battery operated device which has to be improved. Here in this article we have measured performance parameters like power consumption, UNG, Evaluation Delay, standby power and speed of various domino circuits provided for various inputs like 8 &16 input OR gate. When we compared power, delay, and PDP of different topologies of domino circuit design with the simulation results which is performed by using SPICE tool at 32nm CNTFET process technology with supply voltage 0.9V and 27⁰ C of temperature at 100 MHz. All the simulation results is done in CMOS & CNTFET technology, it is observed that saving of average power upto 90.46% with same delay, with improvement of 5.8 × Noise-immunity with scaling of technology.

Low Power Wide Fan-in Domino OR Gate Using CN-MOSFETs

Background & Objective: In this paper, a modified pseudo domino configuration has been proposed to improve the leakage power consumption and Power Delay Product (PDP) of dynamic logic using Carbon Nanotube MOSFETs (CN-MOSFETs). The simulations for proposed and published domino circuits are verified by using Synopsys HSPICE simulator with 32nm CN-MOSFET technology which is provided by Stanford. Methods: The simulation results of the proposed technique are validated for improvement of wide fan-in domino OR gate as a benchmark circuit at 500 MHz clock frequency. Results: The proposed configuration is suitable for cascading of the high performance wide fan-in circuits without any charge sharing. Conclusion: The performance analysis of 8-input OR gate demonstrate that the proposed circuit provides lower static and dynamic power consumption up to 62 and 40% respectively, and PDP improvement is 60% as compared to standard domino circuit.

Improved Domino Logic Circuits and its Application in Wide Fan-In OR Gates

Background: Main concern in efficient VLSI circuit designing is low-power consumption, high-speed and noise tolerance capability. Objective: In this paper, two efficient and high-performance topologies are proposed for cascaded domino logic using carbon nanotube MOSFETs (CN-MOSFETs). The first topology is designed to remove the intermediate charge sharing problem without any keeper circuit, whereas the second one holds the true logic level of the evaluation phase without any voltage drop for next precharge phase. The proposed topologies are suitable for cascading of the high-performance domino circuits. Methods: The proposed domino circuits are tested and verified using Synopsys HSPICE simulator with 32nm CN-MOSFET technology provided by Stanford University. Conclusion: The power delay product of proposed DL-I and DL-II improves by 32.59 % and 40.98 % for 8-input OR gate as compared to standard logic respectively at the clock frequency of 500 MHz. The simulation results validate that the proposed circuits improve the performance of pseudo domino logic with respect to leakage power consumption, delay and unity noise gain.