A Software Emulator for the Modelling and Control of an Activated Sludge Process in a Wastewater Treatment Plant

The design and implementation of a simulator, as a real-time application, for a complex process from the biological treatment stage of a wastewater treatment plant (WWTP), is addressed. More precisely, this emulator was achieved as a software tool that can be later integrated into a more complex SCADA (supervisory control and data acquisition) system of the WWTP Făcăi, Romania. The basic idea is to implement and validate a reduced-order model of the activated sludge process (ASP), initially simulated in the Matlab/Simulink environment (The MathWorks, Inc., Natick, MA, USA). Moreover, an advanced multivariable adaptive control scheme of the ASP is addressed. This software tool can be made to work in parallel with the evolution of the process and can have as input signals measured directly at the process level, possibly following parametric or model adaptations. The software emulator is developed in the LabWindows/CVI programming environment (National Instruments), which offers low-level access to hardware or software systems that have minimal open-architecture facilities. This environment provides versatile drivers and software packages that can facilitate the interaction with software tools developed within some earlier SCADA systems. The structure and the graphical interface of the emulator, some functionalities, experiments, and evolution of main variables are presented.

Enabling Parallelized-QEMU for Hardware/Software Co-Simulation Virtual Platforms

Presently, the trend is to increase the number of cores per chip. This growth is appreciated in Multi-Processor System-On-Chips (MPSoC), composed of more cores in heterogeneous and homogeneous architectures in recent years. Thus, the difficulty of verification of this type of system has been great. The hardware/software co-simulation Virtual Platforms (VP) are presented as a perfect solution to address this complexity, allowing verification by simulation/emulation of software and hardware in the same environment. Some works parallelized the software emulator to reduce the verification times. An example of this parallelization is the QEMU (Quick EMUlator) tool. However, there is no solution to synchronize QEMU with the hardware simulator in this new parallel mode. This work analyzes the current software emulators and presents a new method to allow an external synchronization of QEMU in its parallelized mode. Timing details of the cores are taken into account. In addition, performance analysis of the software emulator with the new synchronization mechanism is presented, using: (1) a boot Linux for MPSoC Zynq-7000 (dual-core ARM Cortex-A9) (Xilinx, San Jose, CA, USA); (2) an FPGA-Linux co-simulation of a power grid monitoring system that is subsequently implemented in an industrial application. The results show that the novel synchronization mechanism does not add any appreciable computational load and enables parallelized-QEMU in hardware/software co-simulation virtual platforms.

PRE-PROCESSING OF ADDITIVE MANUFACTURING INPUT FILES FOR NUMERICAL SIMULATION

In this contribution, we present the concept of a 3D printer software emulator facilitating the creation of a spatial finite element mesh suitable for the printing process simulation. The concept is based on gradual processing of a native 3D printer input file (in a G-code format). This file contains a complete description of manufacturing process consisting of series of individual commands interpreted by a printer. The effect of each command needs to be precisely evaluated to obtain the position of the printer head and the volume of the deposited material in any given time. The calculation is performed in the same way as in the Marlin printer firmware using the trapezoidal motion curves and a command buffer. To represent a computational model, a discrete voxel model with variable edge length and time discretization is used. The volume of deposited material is calculated for each voxel as a function of time. The resulting model is suitable for numerical analysis of the printing process.

Software Defined Networks: a Comparative Study and Quality of Services Evaluation

Software-Defined Network (SDN) as architecture network that separates the control and forwarding functions, so that network operators and administrators can configure the networks in a simple and centrally between thousands of devices. This study is designed and evaluate the Quality of Services (QoS) performances between the two networks employed SDN-based architecture and without SDN-based. MinNet as a software emulator used as a data plane in the network Software Define Network. In this study, comparison of the value of the QoS on the network based on Software Defined Network and traditional network during the test run from the source node is investigated. Network testing by using traffic loads. Traffic loads are used starting from 20Mbps-100Mbps. The result is verified that the QoS analysis of the Software-Defined Network architecture performed better than conventional network architectures. The value of the latency delay on the Software Define Network range between 0,019-0,084ms, and with 0% packet loss when addressed the network traffics of 10-100Mbps.