In-Memory Computing on Resistive RAM Systems Using Majority Operation

Memristors can be used to build nonvolatile memory systems with in-memory computing (IMC) capabilities. A number of prior works demonstrate the design of an IMC-capable memory macro using a memristor crossbar. However, read disturbance limits the use of such memory systems built using a 0-transistor, 1-RRAM (0T1R) structure that suffers from the sneak path problem. In this paper, we introduce a scheme for both memory and logic operations using the 1-transistor, 1-RRAM (1T1R) memristor crossbar, which effectively mitigates the read disturbance problem. The memory array is designed using nMOS transistors and the VTEAM memristor model. The peripheral circuitry like decoders, voltage multiplexers, and sense amplifiers is designed using a 45[Formula: see text]nm CMOS technology node. We introduce a mapping technique to realize arbitrary logic functions using Majority (MAJ) gate operations in the 1T1R crossbar. Through extensive experimentation on benchmark functions, it has been found that the proposed mapping method gives an improvement of 65% or more in terms of the number of time steps required, and 59% or more in terms of energy consumption as compared to some of the recent methods.

Modeling of Statistical Variation Effects on DRAM Sense Amplifier Offset Voltage

With the downscaling in device sizes, process-induced parameter variation has emerged as one of the most serious problems. In particular, the parameter fluctuation of the dynamic random access memory (DRAM) sense amplifiers causes an offset voltage, leading to sensing failure. Previous studies indicate that the threshold voltage mismatch between the paired transistors of a sense amplifier is the most critical factor. In this study, virtual wafers were generated, including statistical VT variation. Then, we numerically investigate the prediction accuracy and reliability of the offset voltage of DRAM wafers using test point measurement for the first time. We expect that this study will be helpful in strengthening the in-line controllability of wafers to secure the DRAM sensing margin.

Comparative Analysis in Terms of Power and Delay of the Different Sense Amplifier Topologies

To read the data from the memory in each of the devices is crucial. In the modern-day VLSI, world need high-speed devices to satisfy the demand for application such as the Internet of Things (IoT) and System on Chip (Soc). We have implemented the different types of existing sense amplifiers to investigate the working and application point of view. Every sense amplifier has its own advantage. Each of the sense amplifiers is focusing basically on the charging and discharging of Bit Line (BL), Bit Line Bar (BLB) in case of Voltage sense and Data Line (DL), Data Line Bar (DLB) in case of current sense. The waveform of the Voltage sense and current sense clearly shown. Performance comparison based on Sensing Delay, Power, and Supply variation at UMC 65nm CMOS technology node using CADENCE Virtuoso tool.

MAS: Maximum Energy-Aware Sense Amplifier Link for Asynchronous Network on Chip

A real-time multiprocessor chip model is also called a Network-on-Chip (NoC), and deals a promising architecture for future systems-on-chips. Even though a lot of Double Tail Sense Amplifiers are used in architectural approach, the existing DTSA with transceiver exhibits a difficulty of consuming more energy than its gouged design during various traffic condition. Novel Low Power pulse Triggered Flip Flop with DTSA is designed in this research to eliminate the difficulty. The Traffic Aware Sense amplifier MAS consists of Sense amplifiers (SA’s), Traffic Generator, and Estimator. Among various SA’S suitable (DTSA and NLPTF -DTSA) SA are selected and information transferred to the receiver. The performance of both DTSA with Transceiver and NLPTF-DTSA with transceiver compared under various traffic conditions. The proposed design (NLPTF-DTSA) is observed on TSMC 90 nm technology, showing 5.92 Gb/s data rate and 0.51 W total link power.