Design of a Capacitance-to-Digital Converter Based on Iterative Delay-Chain Discharge in 180 nm CMOS Technology

The design of advanced miniaturized ultra-low power interfaces for sensors is extremely important for energy-constrained monitoring applications, such as wearable, ingestible and implantable devices used in the health and medical field. Capacitive sensors, together with their correspondent digital-output readout interfaces, make no exception. Here, we analyse and design a capacitance-to-digital converter, based on the recently introduced iterative delay-chain discharge architecture, showing the circuit inner operating principles and the correspondent design trade-offs. A complete design case, implemented in a commercial 180 nm CMOS process, operating at 0.9 V supply for a 0–250 pF input capacitance range, is presented. The circuit, tested by means of detailed electrical simulations, shows ultra-low energy consumption (≤1.884 nJ/conversion), excellent linearity (linearity error 15.26 ppm), good robustness against process and temperature corners (conversion gain sensitivity to process corners variation of 114.0 ppm and maximum temperature sensitivity of 81.9 ppm/∘C in the −40 ∘C, +125 ∘C interval) and medium-low resolution of 10.3 effective number of bits, while using only 0.0192 mm2 of silicon area and employing 2.93 ms for a single conversion.

A Linear VCO Using Single CFA and Analog Multipliers: Quadrature Oscillator Implementation

A new linear voltage-controlled oscillator (LVCO) implementation using single AD-844 CFA with a pair of AD-835 multiplier devices and a pair of grounded capacitors is proposed. The open-loop transfer function of the topology is analyzed wherein the concept of Short-Circuit Natural Frequency (SCNF) is applied to derive the sinusoid oscillator implementation. The proposed oscillator circuit is then restructured to yield a linear voltage-controlled quadrature oscillator (LVCQO) after appropriate cascade with a CFA-based active integrator. The oscillation frequency is linearly tunable ([Formula: see text][Formula: see text]MHz) by the multiplier control voltage ([Formula: see text]. Subsequently, a high-[Formula: see text] selective band-pass (BP) filter is derived. Effects of the CFA port roll-off parameters and its parasitic capacitors ([Formula: see text] had been analyzed to be negligible. Measured oscillator response exhibited a THD [Formula: see text]%, a linearity error ([Formula: see text]% and a phase noise figure of ([Formula: see text]104 dBc/Hz at 24-kHz offset.

Simple Current-Mode Squaring and Square-Rooting Circuits: Applications of MO-CCCCTA

This work provides new designs of simple current-mode squaring and square-rooting circuits using multiple-output current controlled current conveyor transconductance amplifier (MO-CCCCTA) as an active building block. Since the proposed circuits need no other external components, they are capable of high-frequency operation and well fitted for IC fabrication. Furthermore, they are insensitive to ambient temperature and their gains can be controlled easily by adjusting the bias currents of MO-CCCCTA. Additionally, the effects of MO-CCCCTA non-idealities on the designed circuits have also been investigated and discussed. Simulation results generated through PSPICE software using TSMC 0.18 µm CMOS process parameters have been presented to justify the theoretical analysis. The static power consumption, bandwidth, and maximum linearity error in dc transfer characteristic measurement for the square-rooting circuit are found to be 0.17 mW, 445.63 MHz and 1.12 %, while for the squaring circuit they are 0.326 mW, 61.15 MHz and 2.38 %, respectively. The application of the reported circuits as a 2-input vector summation circuit has also been included to strengthen the design ideas. HIGHLIGHTS Simple structures of fully integrable current-mode squarers and square-rooters with low component count and lower power dissipation The circuits are insensitive to temperature drift and their gains can be controlled easily by adjusting the bias currents of MO-CCCCTA Bandwidth, static power dissipation, linearity error of square-rooter are 445.63 MHz, 0.17 mW & ≤ 1.12 %; and for the squarer 61.15 MHz, 0.326 mW & 2.38 %, respectively GRAPHICAL ABSTRACT

Phase Error Analysis and Correction for Crossed-Grating Phase-Shifting Profilometry

Crossed-grating phase-shifting profilometry (CGPSP) has great utility in three-dimensional shape measurement due to its ability to acquire horizontal and vertical phase maps in a single measurement. However, CGPSP is extremely sensitive to the non-linearity effect of a digital fringe projection system, which is not studied in depth yet. In this paper, a mathematical model is established to analyze the phase error caused by the non-linearity effect. Subsequently, two methods used to eliminate the non-linearity error are discussed in detail. To be specific, a double five-step algorithm based on the mathematical model is proposed to passively suppress the second non-linearity. Furthermore, a precoding gamma correction method based on probability distribution function is introduced to actively attenuate the non-linearity of the captured crossed fringe. The comparison results show that the active gamma correction method requires less fringe patterns and can more effectively reduce the non-linearity error compared with the passive method. Finally, employing CGPSP with gamma correction, a faster and reliable inverse pattern projection is realized with less fringe patterns.

MATRIX16: A 16-Channel Low-Power TDC ASIC with 8 ps Time Resolution

This paper presents a highly configurable 16-channel TDC ASIC designed in a commercial 180 nm technology with the following features: time-of-flight and time-over-threshold measurements, 8.6 ps LSB, 7.7 ps jitter, 5.6 ps linearity error, up to 5 MHz of sustained input rate per channel, 9.1 mW of power consumption per channel, and an area of 4.57 mm2. The main contributions of this work are the novel design of the clock interpolation circuitry based on a resistive interpolation mesh circuit and the capability to operate at different supply voltages and operating frequencies, thus providing a compromise between TDC resolution and power consumption.

Design and implementation of 4 bit binary weighted current steering DAC

A compact current-mode Digital-to-Analog converter (DAC) suitable for biomedical application is repesented in this paper .The designed DAC is binary weighted in 180nm CMOS technology with 1.8V supply voltage. In this implementation, authors have focused on calculaton of Non linearity error say INL and DNL for 4 bit DAC having various type of switches: NMOS, PMOS and Transmission Gate. The implemented DAC uses lower area and power compared to unary architecture due to absence of digital decoders. The desired value of Integrated non linearity (INL) and Differential non linearity (DNL) for DAC for are within a range of +0.5LSB. Result obtained in this works for INL and DNL for the case DAC using Transmission Gate is +0.34LSB and +0.38 LSB respectively with 22mW power dissipation.

A portable plantar pressure system: Specifications, design, and preliminary results

BACKGROUND: In recent years, there has been an increasing interest in developing in-shoe foot plantar pressure systems. Although such devices are not novel, devising insole devices for gait analysis is still an important issue. OBJECTIVE: The goal of this study is to develop a new portable system for plantar pressure distribution measurement based on a three-axis accelerometer. METHODS: The portable system includes: PJRC Teensy 3.6 microcontroller with 32-bit ARM Cortex-M4 microprocessor with a clock speed of 180 MHz; HC-11 radio modules (transmitter and receiver); a battery; a fixing band; pressure sensors; MPU-9150 inertial navigation module; and FFC tape. The pressure insole is leather-based and consists of seven layers. It is divided into 16 areas and the outcome of the system is data concerning plantar pressure distribution under foot during gait. The system was tested on 22 healthy volunteer subjects, and the data was compared with a commercially available system: Medilogic. RESULT: The SNR value for the proposed sensor is 28.27 dB. For a range of pressure of 30–100 N, the sensitivity is 0.0066 V/N while the linearity error is 0.05. The difference in plantar pressure from both the portable plantar pressure system and Medilogic is not statistically significant. CONCLUSION: The proposed system could be recommended for research applications both inside and outside of a typical gait laboratory.