Design Project Using 45nm CMOS

<p>this article is aimed to design two impedances matching network to let the source degeneration and common gate amplifier to achieve the ideal characteristic. In the source degeneration case as the resistance is so small, so we just use down converting matching network. As the source degeneration gives us a high resistance , we just match with a up converting network.<b></b></p><p> </p>

Design Project Using 45nm CMOS

<p>this article is aimed to design two impedances matching network to let the source degeneration and common gate amplifier to achieve the ideal characteristic. In the source degeneration case as the resistance is so small, so we just use down converting matching network. As the source degeneration gives us a high resistance , we just match with a up converting network.<b></b></p><p> </p>

Small Delay Tracing Defect Testing

This Small Delay Tracing Defect Testing detect small delay defects by creating internal signal races. The races are created by launching transitions along simultaneous two paths, a reference path and a test path. The arrival times of the transitions on a ‘convergence’ or common gate determine the result of the race. On the output of the convergence gate, a static hazard created by a small delay defect presence on the test path which is directed to the input of a scan-latch. A glitch detector is added to the scan latch which records the presence or absence of the glitch.

Design of a Linear LNA for 5G Applications using 45 nm Technology

A low noise amplifier (LNA) plays a very significant role in communication systems. Despite having a good amplification of the signal it must offer other attributes like noise figure, linearity etc for making the communication system more robust. With the advent of 5G communication, the requirement of a high BW LNA is becoming important. This paper presents the design of a LNA which have a common gate input configuration, an active inductor in place of a passive inductor, common drain amplifier at the output stage and a linearity circuit. Common gate amplifier offers a good voltage amplification while the common drain stage enhances the stability. The active inductor facilitates reduction of the die area paving the way for a cost efficient structure. This proposed design achieves a gain of 15.17dB with substantial enhancement of linearity. A good noise figure of 7dB is obtained while using 11 transistors and eliminating the need of passive inductors. The peak gain is achieved at 3.5GHz

Low Noise Amplifier with Improved Gain and Reduced Noise-Figure in 90nm CMOS Technology

A CMOS low noise amplifier (LNA) for ultra-wideband (UWB) wireless applications is presented in this paper. The proposed CMOS low noise amplifier (LNA) is designed using common-gate (CG) topology as the first stage to achieve ultra-wideband input matching. The common-gate (CG) is cascaded with common- source (CS) topology with current-reused configuration to enhance the gain and noise figure (NF) performance of the LNA with low power. The Buffer stage is used as output matching network to improve the reflection coefficient. The proposed low noise amplifier (LNA) is implemented using CADENCE Virtuoso Analog and Digital Design Environment tool in 90nm CMOS technology. The LNA provides a forward voltage gain or power gain (S21) of 32.34dB , a minimum noise figure of 2dB, a reverse-isolation (S12) of less than - 38.74dB and an output reflection coefficient (S22) of less than -7.4dB for the entire ultra-wideband frequency range. The proposed LNA has an input reflection coefficient (S11) of less than -10dB for the ultra-wideband frequency range. It achieves input referred 1-dB compression point of 78.53dBm and input referred 3-dB compression point of 13dBm. It consumes only 24.226mW of power from a Vdd supply of 0.7V.

Design and simulation of high-swing fully differential telescopic Op-Amp

This article describes the process of design and simulation of a high-swing fully differential telescopic Operational Amplifier (Op-Amp). Due to the Common Gate-Common Source (CG and CS) cascode structure, the gain is very high. To maximize this gain, the load must also be selected such as two current sources. This circuit has the higher voltage in output than current Op-Amps in accordance with desirable characteristics. The loss of power of this operating amplifier are very low and in milliwatts. With use of a power supply of 1.8 V, it achieves a high-swing 1.2 V, a differential gain of 76.333 dB, ω_uGB of 412 MHz, and 50 dB CMRR. This new design through the simulations and analytically shows that the high-swing fully differential telescopic Op-Amp retains its high CMRR even at high frequencies.

CMOS RF Front-Ends For Bluetooth Applications

This project investigates the design of RF front-ends for bluetooth applications. The main objectives in each design are optimized noise figure, power consumption, gain and linearity. The designed cascode LNA achieves 1.37 dB low noise figure through ports matching and maximizes the voltage gain to 11.5 dB. The port isolation reaches to 82 dB. A 2 MHz low IF down-conversion mixer is developed. It employs current injection to reduce the flicker noise of MOSFETs. The total noise figure of the mixer is 17 dB and input referred IIP3 is 4.97 dB. A quadrature mixer constructed by two symmetric Gilbert mixers are discussed. A common-gate class E power amplifier is investigated. Through connecting a L matching network, the output power would be 17.7 dBm at 1.4 V power supply and the power added efficiency PAE and drain efficiency DE are 41% and 42.8 % respectively. To supply two LO frequencies with 90º phase difference, a quadrature voltage controlled oscillator is designed using a series of coupling structure and accumulation mode PMOS varactors. The frequency tuning range is 2.304 GHz ~ 2.54 GHz when the control voltage changes from 0 to 0.7 V. The QVCO exhibits phase noise of -113 dBc/Hz at 600 kHz offset frequency and -119 dBc.Hz at 1 MHz offset frequency. All the circuits were designed in TSMC-0.18μm 1.8 V CMOS technology and simulated using HSPICE RF simulator.

CMOS RF Front-Ends For Bluetooth Applications

This project investigates the design of RF front-ends for bluetooth applications. The main objectives in each design are optimized noise figure, power consumption, gain and linearity. The designed cascode LNA achieves 1.37 dB low noise figure through ports matching and maximizes the voltage gain to 11.5 dB. The port isolation reaches to 82 dB. A 2 MHz low IF down-conversion mixer is developed. It employs current injection to reduce the flicker noise of MOSFETs. The total noise figure of the mixer is 17 dB and input referred IIP3 is 4.97 dB. A quadrature mixer constructed by two symmetric Gilbert mixers are discussed. A common-gate class E power amplifier is investigated. Through connecting a L matching network, the output power would be 17.7 dBm at 1.4 V power supply and the power added efficiency PAE and drain efficiency DE are 41% and 42.8 % respectively. To supply two LO frequencies with 90º phase difference, a quadrature voltage controlled oscillator is designed using a series of coupling structure and accumulation mode PMOS varactors. The frequency tuning range is 2.304 GHz ~ 2.54 GHz when the control voltage changes from 0 to 0.7 V. The QVCO exhibits phase noise of -113 dBc/Hz at 600 kHz offset frequency and -119 dBc.Hz at 1 MHz offset frequency. All the circuits were designed in TSMC-0.18μm 1.8 V CMOS technology and simulated using HSPICE RF simulator.