logic circuit
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2022 ◽  
Author(s):  
Shiqi Liuye ◽  
Shiqiang Cui ◽  
Mengmeng Lu ◽  
Shouzhi Pu

Abstract Photo-controlled fluorescent switching is of great utility in fluorescence sensors, reversible data storage, and logic circuit, based on their modifiable emission intensity and spectra. In this work, a novel photo-controlled reversible fluorescent switching system was constructed based on photochromic diarylethene (DT) molecular modified fluorescent carbon dots (CDs). The fluorescent CDs acted as fluorescent donors and the photochromic diarylethene molecular functioned as acceptors in this fluorescent switching system. The fluorescence modulation efficiency of the fluorescent switching was determined to be 97.1%. The result was attributable to Förster resonance energy transfer (FRET) between the CDs and the diarylethene molecular. The fluorescent switching could undergo 20 cycles without significant decay.


Author(s):  
Philip G. Penketh

AbstractThe possible utilization of biological logic circuit(s) in the integration and regulation of DNA repair is discussed. The author believes this mode of regulation likely applies to many other areas of cell biology; however, there are currently more experimental data to support its involvement in the control of DNA repair. Sequential logic processes always require a clock to orchestrate the orderly processing of events. In the proposed hypothesis, the pulses in the expression of p53 serve this function. Given the many advantages of logic type control, one would expect that in the course of ~ 3 billion years of evolution, where single cell life forms were likely the only forms of life, a biological logic type control system would have evolved to control at least some biological processes. Several other required components in addition to the ‘clock’ have been identified, such as; a method to temporarily inactivate repair processes when they are not required (e.g. the reversible inactivation of MGMT, a suicide repair protein, by phosphorylation); this prevents complex DNA repair systems with potentially overlapping repair functions from interfering with each other.


2021 ◽  
Vol 23 (6) ◽  
pp. 467-474
Author(s):  
Younes Azzoug ◽  
Remus Pusca ◽  
Mohamed Sahraoui ◽  
Abdelkarim Ammar ◽  
Tarek Ameid ◽  
...  

This paper proposes a fault-tolerant control technique against current sensors failure in direct torque controlled induction motors drives, based on a new modification of Luenberger observer for currents estimation and axes transformation for vector rotation. Several important aspects are covered in the proposed algorithm, such as the detection of sensors failure, the isolation of faulty sensors, and the reconfiguration of the control system by a correct estimation. A logic circuit ensures fault detection by analyzing the residual signal between the measured and estimated quantities, while a single observer performs the task of estimating the line currents. In addition, a decision logic circuit isolates the erroneous signal and simultaneously selects the appropriate estimated current signal. An axes transformation ensures rotation from (a,b) to (α,β), which keeps a low-cost control using only two current sensors. The proposed scheme is tested on MATLAB/Simulink environment and experimentally validated in a laboratory prototype mainly containing a dS1104 card and 4 kW induction motor.


2021 ◽  
Vol 2113 (1) ◽  
pp. 012043
Author(s):  
Xinhang Dong ◽  
Boyuan Jing ◽  
Xiang Yang

Abstract 4-bit absolute-value detector (AVD), as one of the basic implementations of bit arithmetic with logic circuits, can help grab a better understanding about digital integrated circuits. Conventional 4-bit AVDs scheme in a multi-comparator and multiplexers, or need to consider multiple situations of overflow and carry-in, both of which could make the final circuit to be complex, labyrinthine and inefficient in the meantime. In this paper, a new design of 4-bit AVD is proposed, the topology of which includes a 2’s complement calculator and a specially designed logic circuit known as chain carry adder (CCA). The whole circuit is concise and the critical path is rigorously considered to make it as short as possible. The delay is set to 1.5 times its minimum, which is positively corresponding to the length of the critical path, the energy accordingly reaches its lower limit. Gate sizing and Device Voltage (VDD) optimization are proceeded for the exact purpose of proving that the circuit energy is minimized.


2021 ◽  
Vol 2113 (1) ◽  
pp. 012039
Author(s):  
Yuefeng Gao ◽  
Qingxing Liu ◽  
Hengji Ye

Abstract At present, artificial intelligence has increasingly become the most promising and essential major. The interdisciplinary cooperation between the integrated circuit and artificial intelligence brings infinite possibilities. In the convolutional neural network area, in order to achieve the valuable output, the comparison between values is often encountered. The output is obtained by comparison between the result after the convolution calculation with the designed threshold. Therefore, our team not only design a 4-bit binary comparator hardware logic circuit to complete the task but also discuss and verify the feasibility and performance characteristics of the program from the perspective of energy and time delay. As for the overall framework, we design a convenient circuit that converts the complement code into the original code and chooses a CLA adder to accomplish this part. Using this kind of adder can ideally help us reduce the time delay at the expense of a complicated circuit schematic. In the comparator part, we design a high-quality circuit framework. The strategy of our circuit is to compare the relationship between the four-bit binary code and the threshold bit by bit from MSB to LSB, which performs better than the original 4-bit comparator, and we design two outputs that can legibly illustrate the relationship between two values. We use logic effort to discuss the normalized delay in our project. Besides, we find the connection between the energy and the delay by calculation. Finally, we design a trade-off function to make the optimization of energy and delay together with respect to voltage.


Micromachines ◽  
2021 ◽  
Vol 12 (11) ◽  
pp. 1344
Author(s):  
Liu Yang ◽  
Yuqi Wang ◽  
Zhiru Wu ◽  
Xiaoyuan Wang

In this paper, a memristor model based on FPGA (field programmable gate array) is proposed, and the circuit of AND gate and OR gate composed of memristors is built by using this model. Combined with the original NOT gate in FPGA, the NAND gate, NOR gate, XOR gate and the XNOR gate are further realized, and then the adder design is completed. Compared with the traditional gate circuit, this model has obvious advantages in size and non-volatility. At the same time, the establishment of this model will add new research methods and tools for memristor simulation research.


2021 ◽  
Author(s):  
Shanshan Li ◽  
Ninghan Zheng ◽  
Yuchao Gao ◽  
Chengbin Quan ◽  
Weidong Liu

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